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參數(shù)資料
| 型號： | W228BH |
| 英文描述： | CPU SYSTEM CLOCK GENERATOR|CMOS|SSOP|56PIN|PLASTIC |
| 中文描述： | CPU系統(tǒng)時鐘發(fā)生器|的CMOS | SSOP封裝| 56PIN |塑料 |
| 文件頁數(shù)： | 1/16頁 |
| 文件大?。?/td> | 172K |
| 代理商： | W228BH |
FTG for Integrated Core Logic with 133-MHz FSB
W228B
Cypress Semiconductor Corporation
Document #: 38-07180 Rev. **
3901 North First Street
San Jose
CA 95134
Revised December 4. 2001
408-943-2600
Features
Maximized EMI suppression using Cypress’s Spread
Spectrum technology
Two copies of CPU clock at 66/100/133 MHz
Thirteen copies of 100-MHz SDRAM clocks
Two copies of PCI clock
One copy of APIC clock at 33 MHz, synchronous to CPU
clock
Two copies of 48-MHz clock (non-spread spectrum) op-
timized for USB reference input and video dot clock
Three copies of 3V 66-MHz fixed clock
One copy of 14.31818-MHz reference clock
Power down control
SMBus interface for turning off unused clocks
Key Specifications
CPU, SDRAM Outputs Cycle-to-Cycle Jitter:.............. 250 ps
APIC, 48-MHz, 3V66, PCI Outputs
Cycle-to-Cycle Jitter:................................................... 500 ps
APIC, SDRAM Output Skew:...................................... 250 ps
CPU, 3V66 Output Skew:............................................175 ps
PCI Output Skew:........................................................500 ps
CPU to SDRAM Skew (@ 133 MHz):.........................
±0.5 ns
CPU to SDRAM Skew (@ 100 MHz):.................4.5 to 5.5 ns
CPU to 3V66 Skew (@ 66 MHz): .......................7.0 to 8.0 ns
3V66 to PCI Skew (3V66 lead):..........................1.5 to 3.5 ns
PCI to APIC Skew: .....................................................±0.5 ns
Intel is a registered trademark of Intel Corporation.
Table 1. Pin Selectable Functions
Tristate#
FSEL0
0
0
0
1
1
0
1
1
1
0
1
1
FSEL1
x
x
0
0
1
1
CPU
SDRAM
Three-state
Test
100 MHz
100 MHz
133 MHz
100 MHz
Three-state
Test
66 MHz
100 MHz
133 MHz
133 MHz
Block Diagram
Pin Configuration
Note:
1.
Internal pull-down resistors present on input marked with *.
Design should not solely rely on internal pull-down resister to
set I/O pin LOW.
[1]
VDDQ3
VDDQ2
PCI0_ICH
XTAL
OSC
PLL REF FREQ
PLL 1
X2
X1
REF0/FSEL1
PCI1
USB
DOT
PLL2
VDDQ3
SMBus
Logic
SDATA
SCLK
3V66_0:1
CPU0:1
FSEL1:0
VDDA
APIC
Divider,
Delay,
and
Phase
Control
Logic
2
VDDQ3
2
SDRAM0:12
13
PWRDWN#
VDDA
3V66_AGP
Tristate#
APIC
VDDQ2
GND
REF0/FSEL1*
VDDQ3
X1
X2
GND
VDDQ3
3V66_0
3V66_1
3V66_AGP
GND
VDDQ3
PCI0_ICH
PCI1
GND
FSEL0
GNDA
VDDA
PWRDWN#
SCLK
SDATA
GND
W
VDDQ2
GND
CPU0
CPU1
GND
SDRAM0
SDRAM1
VDDQ3
GND
SDRAM2
SDRAM3
SDRAM4
VDDQ3
GND
SDRAM5
SDRAM6
VDDQ3
GND
SDRAM7
SDRAM8
SDRAM9
VDDQ3
GND
SDRAM10
SDRAM11
VDDQ3
GND
SDRAM12
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
VDDQ3
USB
DOT
Tristate#
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