參數(shù)資料
型號： W228BH
英文描述： CPU SYSTEM CLOCK GENERATOR|CMOS|SSOP|56PIN|PLASTIC
中文描述： CPU系統(tǒng)時鐘發(fā)生器|的CMOS | SSOP封裝| 56PIN |塑料
文件頁數(shù)： 12/16頁
文件大?。?/td> 172K
代理商： W228BH
W228B
Document #: 38-07180 Rev. **
Page 12 of 16
AC Electrical Characteristics
T
A
= 0
°
C to +70
°
C, V
DDQ3
= 3.3V±5%, V
DDQ2
= 2.5V±5%
f
XTL
= 14.31818 MHz
Spread Spectrum function turned off
AC clock parameters are tested and guaranteed over stated operating conditions using the stated lump capacitive load at the
clock output.
[16]
AC Electrical Characteristics
66.6-MHz Host
Min.
T
Period
Host/CPUCLK Period
15.0
T
HIGH
Host/CPUCLK High Time
5.2
T
LOW
Host/CPUCLK Low Time
5.0
T
RISE
Host/CPUCLK Rise Time
0.4
T
FALL
Host/CPUCLK Fall Time
0.4
Parameter
Description
100-MHz Host
Min.
10.0
3.0
2.8
0.4
0.4
133-MHz Host
Min.
7.5
1.87
1.67
0.4
0.4
Unit
ns
ns
ns
ns
ns
Notes
16
19
Max.
15.5
N/A
N/A
1.6
1.6
Max.
10.5
N/A
N/A
1.6
1.6
Max.
8.0
N/A
N/A
1.6
1.6
20
20
T
Period
T
HIGH
T
LOW
T
RISE
T
FALL
SDRAM CLK Period (100-MHz)
SDRAM CLK High Time (100-MHz)
SDRAM CLK Low Time (100-MHz)
SDRAM CLK Rise Time (100-MHz)
SDRAM CLK Fall Time (100-MHz)
10.0
3.0
2.8
0.4
0.4
10.5
N/A
N/A
1.6
1.6
10.0
3.0
2.8
0.4
0.4
10.5
N/A
N/A
1.6
1.6
10.0
3.0
2.8
0.4
0.4
10.5
N/A
N/A
1.6
1.6
ns
ns
ns
ns
ns
16
19
20
20
T
Period
T
HIGH
T
LOW
T
RISE
T
FALL
SDRAM CLK Period (133-MHz)
SDRAM CLK High Time (133-MHz)
SDRAM CLK Low Time (133-MHz)
SDRAM CLK Rise Time (133-MHz)
SDRAM CLK Fall Time (133-MHz)
7.5
1.87
1.67
0.4
0.4
8.0
N/A
N/A
1.6
1.6
7.5
1.87
1.67
0.4
0.4
8.0
N/A
N/A
1.6
1.6
7.5
1.87
1.67
0.4
.04
8.0
N/A
N/A
1.6
1.6
ns
ns
ns
ns
ns
16
19
20
20
T
Period
T
HIGH
T
LOW
T
RISE
T
FALL
APIC 33-MHz CLK Period
APIC 33-MHz CLK High Time
APIC 33-MHz CLK Low Time
APIC CLK Rise Time
APIC CLK Fall Time
30.0
12.0
12.0
0.4
0.4
N/A
N/A
N/A
1.6
1.6
30.0
12.0
12.0
0.4
0.4
N/A
N/A
N/A
1.6
1.6
30.0
12.0
12.0
0.4
0.4
N/A
N/A
N/A
1.6
1.6
ns
ns
ns
ns
ns
16
19
20
20
T
Period
T
HIGH
T
LOW
T
RISE
T
FALL
3V66 CLK Period
3V66 CLK High Time
3V66 CLK Low Time
3V66 CLK Rise Time
3V66 CLK Fall Time
15.0
5.25
5.05
0.5
0.5
16.0
N/A
N/A
2.0
2.0
15.0
5.25
5.05
0.5
0.5
16.0
N/A
N/A
2.0
2.0
15.0
5.25
5.05
0.5
0.5
16.0
N/A
N/A
2.0
2.0
ns
ns
ns
ns
ns
16, 18
19
20
20
T
Period
T
HIGH
T
LOW
T
RISE
T
FALL
Notes:
16. Period, jitter, offset, and skew measured on rising edge at 1.25 for 2.5V clocks and at 1.5V for 3.3V clocks.
17. T
HIGH
is measured at 2.0V for 2.5V outputs, 2.4V for 3.3V outputs.
18. T
is measured at 0.4V for all outputs.
19. The time specified is measured from when V
DDQ3
achieves its nominal operating level (typical condition V
DDQ3
= 3.3V) until the frequency output is stable
and operating within specification.
20. T
and T
FALL
are measured as a transition through the threshold region V
ol
= 0.4V and V
oh
= 2.0V (1 mA) JEDEC specification for 2.5V outputs and V
OL
= 0.4V and V
OH
= 2.4V for 3.3V outputs.
PCI CLK Period
PCI CLK High Time
PCI CLK Low Time
PCI CLK Rise Time
PCI CLK Fall Time
30.0
12.0
12.0
0.5
0.5
N/A
N/A
N/A
2.0
2.0
30.0
12.0
12.0
0.5
0.5
N/A
N/A
N/A
2.0
2.0
30.0
12.0
12.0
0.5
0.5
N/A
N/A
N/A
2.0
2.0
ns
ns
ns
ns
ns
16, 17
19
20
20
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