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參數(shù)資料
| 型號： | W228BH |
| 英文描述： | CPU SYSTEM CLOCK GENERATOR|CMOS|SSOP|56PIN|PLASTIC |
| 中文描述： | CPU系統(tǒng)時鐘發(fā)生器|的CMOS | SSOP封裝| 56PIN |塑料 |
| 文件頁數(shù)： | 8/16頁 |
| 文件大小： | 172K |
| 代理商： | W228BH |
W228B
Document #: 38-07180 Rev. **
Page 8 of 16
Serial Data Interface
The W228B features a two-pin, serial data interface that can
be used to configure internal register settings that control par-
ticular device functions.
Data Protocol
The clock driver serial protocol accepts only block writes from
the controller. The bytes must be accessed in sequential order
from lowest to highest byte with the ability to stop after any
complete byte has been transferred. Indexed bytes are not
allowed.
A block write begins with a slave address and a write condition.
After the command code the core logic issues a byte count
which describes how many more bytes will follow in the mes-
sage. If the host had 20 bytes to send, the first byte would be
the number 20 (14h), followed by the 20 bytes of data. The
byte count may not be 0. A block write command is allowed to
transfer a maximum of 32 data bytes. The slave receiver ad-
dress for W228B is 11010010.
Figure 9
shows an example of
a block write.
The command code and the byte count bytes are required as
the first two bytes of any transfer. W228B expects a command
code of 0000 0000. The byte count byte is the number of ad-
ditional bytes required for the transfer, not counting the com-
mand code and byte count bytes. Additionally, the byte count
byte is required to be a minimum of 1 byte and a maximum of
32 bytes to satisfy the above requirement.
Table 4
shows an
example of a possible byte count value.
A transfer is considered valid after the acknowledge bit corre-
sponding to the byte count is read by the controller. The com-
mand code and byte count bytes are ignored by the W228B.
However, these bytes must be included in the data write se-
quence to maintain proper byte allocation.
Notes:
12. The acknowledgment bit is returned by the slave/receiver (W228B).
13. Data Bytes 3 to 7 are reserved.
1 bit
7 bits
1
1
8 bits
1
Start bit
Slave Address
R/W
Ack
Command Code
Ack
Byte Count = N
Ack
Data Byte 1
Ack
Data Byte 2
Ack
...
Data Byte N
Ack
Stop
1 bit
8 bits
1
8 bits
1
8 bits
1
1
Figure 9. An Example of a Block Write
[12]
Table 4. Example of Possible Byte Count Value
Byte Count Byte
MSB
0000
0000
0000
0000
0000
0000
0000
0000
0010
Notes
LSB
0000
0001
0010
0011
0100
0101
0110
0111
0000
Not allowed. Must have at least one byte
Data for functional and frequency select register (currently byte 0 in spec)
Reads first two bytes of data (byte 0 then byte 1)
Reads first three bytes (byte 0, 1, 2 in order)
Reads first four bytes (byte 0, 1, 2, 3 in order)
Reads first five bytes (byte 0, 1, 2, 3, 4 in order)
[13]
Reads first six bytes (byte 0, 1, 2, 3, 4, 5 in order)
[13]
Reads first seven bytes (byte 0, 1, 2, 3, 4, 5, 6 in order)
Max. byte count supported = 32
Table 5. Serial Data Interface Control Functions Summary
Control Function
Output Disable
Any individual clock output(s) can be disabled.
Disabled outputs are actively held LOW.
Description
Common Application
Unused outputs are disabled to reduce EMI and sys-
tem power. Examples are clock outputs to unused
PCI slots.
For EMI reduction.
Spread Spectrum
Enabling
(Reserved)
Enables or disables spread spectrum clocking.
Reserved function for future device revision or
production device testing.
No user application. Register bit must be written as 0.
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