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參數資料
| 型號： | W228BH |
| 英文描述： | CPU SYSTEM CLOCK GENERATOR|CMOS|SSOP|56PIN|PLASTIC |
| 中文描述： | CPU系統(tǒng)時鐘發(fā)生器|的CMOS | SSOP封裝| 56PIN |塑料 |
| 文件頁數： | 13/16頁 |
| 文件大?。?/td> | 172K |
| 代理商： | W228BH |
W228B
Document #: 38-07180 Rev. **
Page 13 of 16
tp
ZL
, tp
ZH
tp
LZ
, tp
ZH
t
stable
Output Enable Delay (All outputs)
Output Disable Delay (All outputs)
All Clock Stabilization from Power-Up
1.0
1.0
10.0
10.0
3
1.0
1.0
10.0
10.0
3
1.0
1.0
10.0
10.0
3
ns
ns
ms
Group Skew and Jitter Limits
Output Group
CPU
SDRAM
APIC
48MHz
3V66
PCI
REF
Pin-Pin Skew Max.
175 ps
250 ps
250 ps
250 ps
175 ps
500 ps
N/A
Cycle-Cycle Jitter
250 ps
250 ps
500 ps
500 ps
500 ps
500 ps
1000 ps
Duty Cycle
45/55
45/55
45/55
45/55
45/55
45/55
45/55
Nom. Vdd
2.5V
3.3V
2.5V
3.3V
3.3V
3.3V
3.3V
Skew, Jitter
Measure Point
1.25V
1.5V
1.25V
1.5V
1.5V
1.5V
1.5V
AC Electrical Characteristics
(continued)
Parameter
Description
66.6-MHz Host
Min.
100-MHz Host
Min.
133-MHz Host
Min.
Unit
Notes
Max.
Max.
Max.
Clock Output Wave
2.5V Clocking
Interface
3.3V Clocking
Interface
Test Point
Test Load
T
PERIOD
Duty Cycle
T
HIGH
2.0
1.25
0.4
T
LOW
T
RISE
T
FALL
T
LOW
T
RISE
T
FALL
T
PERIOD
Duty Cycle
T
HIGH
2.4
1.5
0.4
Output
Buffer
Figure 10. Output Buffer
Ordering Information
Ordering Code
W228B
Package
Name
H
Package Type
56-pin SSOP (300 mils)
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