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參數(shù)資料
| 型號： | W228BH |
| 英文描述： | CPU SYSTEM CLOCK GENERATOR|CMOS|SSOP|56PIN|PLASTIC |
| 中文描述： | CPU系統(tǒng)時(shí)鐘發(fā)生器|的CMOS | SSOP封裝| 56PIN |塑料 |
| 文件頁數(shù)： | 2/16頁 |
| 文件大小： | 172K |
| 代理商： | W228BH |
W228B
Document #: 38-07180 Rev. **
Page 2 of 16
Pin Definitions
Pin Name
REF0/FSEL1
Pin No.
4
Pin
Type
I/O
Pin Description
Reference Clock:
3.3V 14.318-MHz clock output. This pin also serves as a strap
option for CPU frequency selection. See
Table 1
for detailed descriptions.
Crystal Input:
This pin has dual functions. It can be used as an external
14.318-MHz crystal connection or as an external reference frequency input.
Crystal Output:
A connection for an external 14.318-MHz crystal. If using an ex-
ternal reference, this pin must be left unconnected.
PCI Clock 0 through 1:
3.3V 33-MHz PCI clock outputs. PCI1 can be individually
turned off via SMBus interface.
66-MHz Clock Output:
3.3V fixed 66-MHz clock.
X1
6
I
X2
7
O
PCI0_ICH,
PCI1
3V66_0:2,
3V66_AGP
USB
DOT
Tristate#,
FSEL0
PWRDWN#
15, 16
O
10, 11, 12
O
26
27
O
O
I
USB Clock Output:
3.3V fixed 48-MHz, non-spread spectrum USB clock output.
Dot Clock Output:
3.3V 48-MHz, non-spread spectrum signal.
Clock Function Selection pins:
LVTTL-compatible input to select device func-
tions. See
Table 1
for detailed descriptions.
Power-Down Control:
LVTTL-compatible asynchronous input that places the de-
vice in power-down mode when held LOW.
CPU Clock Outputs:
Clock outputs for the host bus interface and integrated test
port. Output frequencies run at 66 MHz, 100 MHz, or 133 MHz depending on the
configuration of SEL0:1 and SEL133. Voltage swing set by VDDQ2.
SDRAM Clock Outputs:
3.3V outputs running at 100 MHz. SDRAM0:12 can be
individually turned off via SMBus interface.
28, 18
21
I
CPU0:1
54, 53
O
SDRAM0:12
51, 50, 47, 46,
45, 42, 41, 38,
37, 36, 33, 32,
29
1
O
APIC
O
Synchronous APIC Clock Outputs:
Clock outputs running synchronous with the
PCI clock outputs (33 MHz). Voltage swing set by VDDQ2.
Data pin for SMBus circuitry.
Clock pin for SMBus circuitry.
3.3V Power Connection:
Power supply for SDRAM output buffers, PCI output
buffers, 3V66 output buffers, reference output buffers, and 48-MHz output buffers.
Connect to 3.3V.
3.3V Power Connection:
Power supply for core logic, PLL circuitry. Connect to
3.3V.
2.5V Power Connection:
Power supply for IOAPIC and CPU output buffers. Con-
nect to 2.5V or 3.3V.
Ground Connections:
Connect all ground pins to the common system ground
plane.
SDATA
SCLK
VDDQ3
23
22
I/O
I
P
5, 9, 14, 25, 31,
35, 40, 44, 49
VDDA
20
P
VDDQ2
2, 56
P
GND
3, 8, 13, 17, 24,
30, 34, 39, 43,
48, 52, 55
19
G
GNDA
G
Ground Connections:
Connect all ground pins to the common system ground
plane.
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