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參數(shù)資料
| 型號(hào)： | W228BH |
| 英文描述： | CPU SYSTEM CLOCK GENERATOR|CMOS|SSOP|56PIN|PLASTIC |
| 中文描述： | CPU系統(tǒng)時(shí)鐘發(fā)生器|的CMOS | SSOP封裝| 56PIN |塑料 |
| 文件頁(yè)數(shù)： | 6/16頁(yè) |
| 文件大小： | 172K |
| 代理商： | W228BH |
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W228B
Document #: 38-07180 Rev. **
Page 6 of 16
Power Down Control
W228B provides one PWRDWN# signal to place the device in low-power mode. In low-power mode, the PLLs are turned off and
all clock outputs are driven LOW.
Notes:
8.
9.
10. PWRDWN# is an asynchronous input and metastable conditions could exist. This signal is synchronized inside W228B.
“
don
’
t care
”
states.
11.
Diagrams shown with respect to 100 MHz. Similar operation when CPU is 66 MHz.
Once the PWRDWN# signal is sampled LOW for two consecutive rising edges of CPU, clocks of interest will be held LOW on the next HIGH-to-LOW transition.
Table 3. W228B Maximum Allowed Current
W228B
Condition
Max. 2.5V supply consumption
Max. discrete cap loads,
V
= 2.625V
All static inputs = V
DDQ3
or V
SS
100
μ
A
Max. 3.3V supply consumption
Max. discrete cap loads
V
= 3.465V
All static inputs = V
DDQ3
or V
SS
500
μ
A
Powerdown Mode
(PWRDWN# = 0)
Full Active 66 MHz
FSEL1:0 = 00 (PWRDWN# =1)
Full Active 100 MHz
FSEL1:0 = 01 (PWRDWN# =1)
Full Active 133 MHz
FSEL1:0 = 11 (PWRDWN# =1)
30 mA
280 mA
40 mA
280 mA
50 mA
400 mA
1
2
Center
0 ns
25 ns
50 ns
75 ns
VCO Internal
CPU 100-MHz
3V66 66-MHz
PCI 33-MHz
APIC 33-MHz
PwrDwn
SDRAM 100-MHz
REF 14.318-MHz
USB 48-MHz
Figure 6. W228B PWRDWN# Timing Diagram
[8, 9, 10, 11]
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