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參數(shù)資料
| 型號： | W25Q80BVSNAP |
| 廠商： | WINBOND ELECTRONICS CORP |
| 元件分類： | PROM |
| 英文描述： | 8M X 1 SPI BUS SERIAL EEPROM, PDSO8 |
| 封裝： | 0.150 INCH, GREEN, PLASTIC, SOIC-8 |
| 文件頁數(shù)： | 25/75頁 |
| 文件大小： | 1055K |
| 代理商： | W25Q80BVSNAP |
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W25Q80BV
Publication Release Date: October 06, 2010
- 31 -
Revision D
9.2.15 Fast Read Quad I/O (EBh)
The Fast Read Quad I/O (EBh) instruction is similar to the Fast Read Dual I/O (BBh) instruction except
that address and data bits are input and output through four pins IO0, IO1, IO2 and IO3 and four Dummy
clock are required prior to the data output. The Quad I/O dramatically reduces instruction overhead
allowing faster random access for code execution (XIP) directly from the Quad SPI. The Quad Enable bit
(QE) of Status Register-2 must be set to enable the Fast Read Quad I/O Instruction.
Fast Read Quad I/O with “Continuous Read Mode”
The Fast Read Quad I/O instruction can further reduce instruction overhead through setting the
“Continuous Read Mode” bits (M7-0) after the input Address bits (A23-0), as shown in figure 14a. The
upper nibble of the (M7-4) controls the length of the next Fast Read Quad I/O instruction through the
inclusion or exclusion of the first byte instruction code. The lower nibble bits of the (M3-0) are don’t care
(“x”). However, the IO pins should be high-impedance prior to the falling edge of the first data out clock.
If the “Continuous Read Mode” bits M5-4 = (1,0), then the next Fast Read Quad I/O instruction (after /CS
is raised and then lowered) does not require the EBh instruction code, as shown in figure 14b. This
reduces the instruction sequence by eight clocks and allows the Read address to be immediately entered
after /CS is asserted low. If the “Continuous Read Mode” bits M5-4 do not equal to (1,0), the next
instruction (after /CS is raised and then lowered) requires the first byte instruction code, thus returning to
normal operation. A “Continuous Read Mode” Reset instruction can also be used to reset (M7-0) before
issuing normal instructions (See 9.2.20 for detail descriptions).
M7-0
/CS
CLK
Mode 0
Mode 3
0
1
IO
0
IO
1
IO
2
IO
3
2
3
4
5
20
16
12
8
21
17
22
18
23
19
13
9
14
10
15
11
A23-16
6
7
8
9
4
0
5
1
6
2
7
3
A15-8
A7-0
4
Byte 1
Byte 2
0
5
1
6
2
7
3
4
0
5
1
6
2
7
3
4
0
5
1
6
2
7
3
10
11
12
13
14
4
5
6
7
IOs switch from
Input to Output
Byte 3
15
16
17
18
19
20
21
22
23
Dummy
Instruction (EBh)
Figure 14a. Fast Read Quad I/O Instruction Sequence (Initial instruction or previous M5-4
≠ 10)
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相關代理商/技術參數(shù) |
參數(shù)描述 |
|---|---|
| W25Q80BVSNIG | 功能描述:IC SPI FLASH 8MBIT 8SOIC RoHS:是 類別:集成電路 (IC) >> 存儲器 系列:SpiFlash® 標準包裝:2,000 系列:- 格式 - 存儲器:RAM 存儲器類型:SRAM - 異步 存儲容量:256K (32K x 8) 速度:15ns 接口:并聯(lián) 電源電壓:3 V ~ 3.6 V 工作溫度:-40°C ~ 85°C 封裝/外殼:28-TSSOP（0.465"，11.8mm 寬） 供應商設備封裝:28-TSOP 包裝:帶卷 (TR) 其它名稱:71V256SA15PZGI8 |
| W25Q80BVSNIG TR | 制造商:Winbond Electronics Corp 功能描述: 制造商:Winbond Electronics Corp 功能描述:IC FLASH 8MBIT 104MHZ 8SOIC |
| W25Q80BVSNIP | 制造商:WINBOND 制造商全稱:Winbond 功能描述:8M-BIT SERIAL FLASH MEMORY WITH DUAL AND QUAD SPI |
| W25Q80BVSSAG | 制造商:WINBOND 制造商全稱:Winbond 功能描述:8M-BIT SERIAL FLASH MEMORY WITH DUAL AND QUAD SPI |
| W25Q80BVSSAP | 制造商:WINBOND 制造商全稱:Winbond 功能描述:8M-BIT SERIAL FLASH MEMORY WITH DUAL AND QUAD SPI |
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