參數(shù)資料
型號(hào): W25Q80BVSNAP
廠商: WINBOND ELECTRONICS CORP
元件分類(lèi): PROM
英文描述: 8M X 1 SPI BUS SERIAL EEPROM, PDSO8
封裝: 0.150 INCH, GREEN, PLASTIC, SOIC-8
文件頁(yè)數(shù): 35/75頁(yè)
文件大小: 1055K
代理商: W25Q80BVSNAP
W25Q80BV
- 40 -
9.2.22 Quad Input Page Program (32h)
The Quad Page Program instruction allows up to 256 bytes of data to be programmed at previously
erased (FFh) memory locations using four pins: IO0, IO1, IO2, and IO3. The Quad Page Program can
improve performance for PROM Programmer and applications that have slow clock speeds <5MHz.
Systems with faster clock speed will not realize much benefit for the Quad Page Program instruction
since the inherent page program time is much greater than the time it take to clock-in the data.
To use Quad Page Program the Quad Enable in Status Register-2 must be set (QE=1). A Write Enable
instruction must be executed before the device will accept the Quad Page Program instruction (Status
Register-1, WEL=1). The instruction is initiated by driving the /CS pin low then shifting the instruction
code “32h” followed by a 24-bit address (A23-A0) and at least one data byte, into the IO pins. The /CS pin
must be held low for the entire length of the instruction while data is being sent to the device. All other
functions of Quad Page Program are identical to standard Page Program. The Quad Page Program
instruction sequence is shown in figure 20.
/CS
CLK
Mode 0
Mode 3
0
1
2
3
4
5
6
7
Instruction (32h)
8
9
10
28
29
30
32
33
34
35
36
37
4
0
24-Bit Address
23
22
21
3
2
1
0
*
31
/CS
CLK
5
1
Byte 1
6
2
7
3
4
0
5
1
6
2
7
3
4
0
5
1
6
2
7
3
4
0
5
1
6
2
7
3
Byte 2
Byte 3
Byte
256
0
4
0
5
1
6
2
7
3
4
0
5
1
6
2
7
3
4
0
5
1
6
2
7
3
53
6
53
7
53
8
53
9
54
0
54
1
54
2
54
3
Mode 0
Mode 3
Byte
253
Byte
254
Byte
255
IO
0
IO
1
IO
2
IO
3
IO
0
IO
1
IO
2
IO
3
***
****
= MSB
*
Figure 20. Quad Input Page Program Instruction Sequence Diagram
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