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參數(shù)資料
型號(hào): XA3S400A-4FTG256Q
廠(chǎng)商: Xilinx Inc
文件頁(yè)數(shù): 14/57頁(yè)
文件大?。?/td> 0K
描述: IC FPGA SPARTAN-3A 400K 256FTBGA
產(chǎn)品培訓(xùn)模塊: Extended Spartan 3A FPGA Family
標(biāo)準(zhǔn)包裝: 1
系列: Spartan®-3A XA
LAB/CLB數(shù): 896
邏輯元件/單元數(shù): 8064
RAM 位總計(jì): 368640
輸入/輸出數(shù): 195
門(mén)數(shù): 400000
電源電壓: 1.14 V ~ 1.26 V
安裝類(lèi)型: 表面貼裝
工作溫度: -40°C ~ 125°C
封裝/外殼: 256-LBGA
供應(yīng)商設(shè)備封裝: 256-FTBGA
XA Spartan-3A Automotive FPGA Family Data Sheet
DS681 (v2.0) April 22, 2011
Product Specification
21
TIOICKPD
Time from the active transition at
the ICLK input of the Input
Flip-Flop (IFF) to the point where
data must be held at the Input pin.
The Input Delay is programmed.
LVCMOS25(3)
1
XA3S200A
–1.51
ns
2
–2.09
ns
3
–2.40
ns
4
–2.68
ns
5
–2.56
ns
6
–2.99
ns
7
–3.29
ns
8
–3.61
ns
1
XA3S400A
–1.12
ns
2
–1.70
ns
3
–2.08
ns
4
–2.38
ns
5
–2.23
ns
6
–2.69
ns
7
–3.08
ns
8
–3.35
ns
1
XA3S700A
–1.67
ns
2
–2.27
ns
3
–2.59
ns
4
–2.92
ns
5
–2.89
ns
6
–3.22
ns
7
–3.52
ns
8
–3.81
ns
1
XA3S1400A
–1.60
ns
2
–2.06
ns
3
–2.46
ns
4
–2.86
ns
5
–2.88
ns
6
–3.24
ns
7
–3.55
ns
8
–3.89
ns
Set/Reset Pulse Width
TRPW_IOB
Minimum pulse width to SR control
input on IOB
All
1.61
ns
Notes:
1.
The numbers in this table are tested using the methodology presented in Table 26 and are based on the operating conditions set forth in
2.
This setup time requires adjustment whenever a signal standard other than LVCMOS25 is assigned to the data Input. If this is true, add the
appropriate Input adjustment from Table 22.
3.
These hold times require adjustment whenever a signal standard other than LVCMOS25 is assigned to the data Input. If this is true, subtract
the appropriate Input adjustment from Table 22. When the hold time is negative, it is possible to change the data before the clock’s active
edge.
Table 20: Setup and Hold Times for the IOB Input Path (Cont’d)
Symbol
Description
Conditions
IFD_
DELAY_
VALUE
Device
Speed Grade: -4
Units
Min
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