參數(shù)資料
型號(hào): XA3S400A-4FTG256Q
廠商: Xilinx Inc
文件頁(yè)數(shù): 6/57頁(yè)
文件大?。?/td> 0K
描述: IC FPGA SPARTAN-3A 400K 256FTBGA
產(chǎn)品培訓(xùn)模塊: Extended Spartan 3A FPGA Family
標(biāo)準(zhǔn)包裝: 1
系列: Spartan®-3A XA
LAB/CLB數(shù): 896
邏輯元件/單元數(shù): 8064
RAM 位總計(jì): 368640
輸入/輸出數(shù): 195
門(mén)數(shù): 400000
電源電壓: 1.14 V ~ 1.26 V
安裝類型: 表面貼裝
工作溫度: -40°C ~ 125°C
封裝/外殼: 256-LBGA
供應(yīng)商設(shè)備封裝: 256-FTBGA
XA Spartan-3A Automotive FPGA Family Data Sheet
DS681 (v2.0) April 22, 2011
Product Specification
14
Table 13: Recommended Operating Conditions for User I/Os Using Differential Signal Standards
IOSTANDARD Attribute
VCCO for Drivers(1)
VID
VICM(2)
Min (V)
Nom (V)
Max (V)
Min (mV)
Nom (mV) Max (mV)
Min (V)
Nom (V)
Max (V)
2.25
2.5
2.75
100
350
600
0.3
1.25
2.35
3.0
3.3
3.6
100
350
600
0.3
1.25
2.35
2.25
2.5
2.75
100
300
–0.3
1.3
2.35
MINI_LVDS_25(3)
2.25
2.5
2.75
200
600
0.3
1.2
1.95
MINI_LVDS_33(3)
3.0
3.3
3.6
200
600
0.3
1.2
1.95
LVPECL_25(5)
Inputs Only
100
800
1000
0.3
1.2
1.95
LVPECL_33(5)
Inputs Only
100
800
1000
0.3
1.2
2.8(6)
RSDS_25(3)
2.25
2.5
2.75
100
200
0.3
1.2
1.5
RSDS_33(3)
3.0
3.3
3.6
100
200
0.3
1.2
1.5
TMDS_33(3,4,7)
3.14
3.3
3.47
150
1200
2.7
–3.23
2.25
2.5
2.75
100
400
0.2
–2.3
3.0
3.3
3.6
100
400
0.2
–2.3
DIFF_HSTL_I_18
1.7
1.8
1.9
100
–0.8
–1.1
DIFF_HSTL_II_18(8)
1.7
1.8
1.9
100
–0.8
–1.1
DIFF_HSTL_III_18
1.7
1.8
1.9
100
–0.8
–1.1
DIFF_HSTL_I
1.4
1.5
1.6
100
–0.68
0.9
DIFF_HSTL_III
1.4
1.5
1.6
100
–0.9
DIFF_SSTL18_I
1.7
1.8
1.9
100
–0.7
–1.1
DIFF_SSTL18_II(8)
1.7
1.8
1.9
100
–0.7
–1.1
DIFF_SSTL2_I
2.3
2.5
2.7
100
–1.0
–1.5
DIFF_SSTL2_II(8)
2.3
2.5
2.7
100
–1.0
–1.5
DIFF_SSTL3_I
3.0
3.3
3.6
100
–1.1
–1.9
DIFF_SSTL3_II
3.0
3.3
3.6
100
–1.1
–1.9
Notes:
1.
The VCCO rails supply only differential output drivers, not input circuits.
2.
VICM must be less than VCCAUX.
3.
These true differential output standards are supported only on FPGA banks 0 and 2. Inputs are unrestricted. See the chapter "Using I/O
Resources" in UG331.
4.
5.
LVPECL is supported on inputs only, not outputs. LVPECL_33 requires VCCAUX=3.3V ± 10%.
6.
LVPECL_33 maximum VICM = the lower of 2.8V or VCCAUX –(VID / 2)
7.
Requires VCCAUX = 3.3V ± 10% for inputs. (VCCAUX – 300 mV) VICM (VCCAUX – 37 mV)
8.
These higher-drive output standards are supported only on FPGA banks 1 and 3. Inputs are unrestricted. See the chapter "Using I/O
Resources" in UG331.
9.
VREF inputs are used for the DIFF_SSTL and DIFF_HSTL standards. The VREF settings are the same as for the single-ended versions in
Table 11. Other differential standards do not use VREF.
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