參數(shù)資料
型號(hào): XA3S400A-4FTG256Q
廠商: Xilinx Inc
文件頁數(shù): 5/57頁
文件大?。?/td> 0K
描述: IC FPGA SPARTAN-3A 400K 256FTBGA
產(chǎn)品培訓(xùn)模塊: Extended Spartan 3A FPGA Family
標(biāo)準(zhǔn)包裝: 1
系列: Spartan®-3A XA
LAB/CLB數(shù): 896
邏輯元件/單元數(shù): 8064
RAM 位總計(jì): 368640
輸入/輸出數(shù): 195
門數(shù): 400000
電源電壓: 1.14 V ~ 1.26 V
安裝類型: 表面貼裝
工作溫度: -40°C ~ 125°C
封裝/外殼: 256-LBGA
供應(yīng)商設(shè)備封裝: 256-FTBGA
XA Spartan-3A Automotive FPGA Family Data Sheet
DS681 (v2.0) April 22, 2011
Product Specification
13
Differential I/O Standards
Differential Input Pairs
HSTL_I(4)
8–8
0.4
VCCO – 0.4
–8
0.4
VCCO – 0.4
HSTL_I_18
8
–8
0.4
VCCO – 0.4
16
–16(7)
0.4
VCCO – 0.4
HSTL_III_18
–8
0.4
VCCO – 0.4
SSTL18_I
6.7
–6.7
VTT – 0.475
VTT + 0.475
SSTL18_II(4)
13.4
–13.4
VTT – 0.475
VTT + 0.475
SSTL2_I
8.1
–8.1
VTT – 0.61
VTT + 0.61
16.2
–16.2
VTT – 0.80
VTT + 0.80
SSTL3_I
8
–8
VTT – 0.6
VTT + 0.6
SSTL3_II
16
–16
VTT – 0.8
VTT + 0.8
Notes:
1.
The numbers in this table are based on the conditions set forth in Table 8 and Table 11.
2.
Descriptions of the symbols used in this table are as follows:
IOL the output current condition under which VOL is tested
IOH the output current condition under which VOH is tested
VOL the output voltage that indicates a Low logic level
VOH the output voltage that indicates a High logic level
VIL the input voltage that indicates a Low logic level
VIH the input voltage that indicates a High logic level
VCCO the supply voltage for output drivers
VREF the reference voltage for setting the input switching threshold
VTT the voltage applied to a resistor termination
3.
For the LVCMOS and LVTTL standards: the same VOL and VOH limits apply for both the Fast and Slow slew attributes.
4.
These higher-drive output standards are supported only on FPGA banks 1 and 3. Inputs are unrestricted. See the chapter "Using I/O
Resources" in UG331.
5.
Tested according to the relevant PCI specifications. For information on PCI IP solutions, see
input-only pins. The PCIX IOSTANDARD is available and has equivalent characteristics, but no PCI-X IP is supported.
6.
DE-RATE by 20% for TJ above 100°C
7.
DE-RATE by 5% for TJ above 100°C
X-Ref Target - Figure 4
Figure 4: Differential Input Voltages
Table 12: DC Characteristics of User I/Os Using Single-Ended Standards (Cont’d)
IOSTANDARD Attribute
Test Conditions
Logic Level Characteristics
IOL (mA)
IOH (mA)
VOL Max (V)
VOH Min (V)
DS681_03_041111
V
INN
V
INP
GND level
50%
V
ICM
V
ICM = Input common mode voltage =
V
ID
V
INP
Internal
Logic
Differential
I/O Pair Pins
V
INN
N
P
2
V
INP
+ V
INN
V
ID = Differential input voltage =
V
INP
- V
INN
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