參數(shù)資料
型號: XA3SD1800A-4FGG676I
廠商: Xilinx Inc
文件頁數(shù): 21/58頁
文件大?。?/td> 0K
描述: SPARTAN-3ADSP FPGA 1800K 676FBGA
產(chǎn)品培訓(xùn)模塊: Extended Spartan 3A FPGA Family
標(biāo)準(zhǔn)包裝: 40
系列: Spartan®-3A DSP XA
LAB/CLB數(shù): 4160
邏輯元件/單元數(shù): 37440
RAM 位總計(jì): 1548288
輸入/輸出數(shù): 519
門數(shù): 1800000
電源電壓: 1.14 V ~ 1.26 V
安裝類型: 表面貼裝
工作溫度: -40°C ~ 100°C
封裝/外殼: 676-BGA
供應(yīng)商設(shè)備封裝: 676-FBGA(27x27)
配用: 122-1574-ND - KIT DEVELOPMENT SPARTAN 3ADSP
XA Spartan-3A DSP Automotive FPGA Family Data Sheet
DS705 (v2.0) April 18, 2011
Product Specification
28
Differential Standards
LVDS_25
1.49
ns
LVDS_33
0.46
ns
BLVDS_25
0.11
ns
MINI_LVDS_25
1.11
ns
MINI_LVDS_33
0.41
ns
LVPECL_25
Input Only
LVPECL_33
RSDS_25
1.72
ns
RSDS_33
0.64
ns
TMDS_33
0.46
ns
PPDS_25
1.28
ns
PPDS_33
0.88
ns
DIFF_HSTL_I_18
0.43
ns
DIFF_HSTL_II_18
0.41
ns
DIFF_HSTL_III_18
0.36
ns
DIFF_HSTL_I
1.01
ns
DIFF_HSTL_III
1.16
ns
DIFF_SSTL18_I
0.49
ns
DIFF_SSTL18_II
0.41
ns
DIFF_SSTL2_I
0.91
ns
DIFF_SSTL2_II
0.10
ns
DIFF_SSTL3_I
1.18
ns
DIFF_SSTL3_II
0.28
ns
Notes:
1.
The numbers in this table are tested using the methodology presented in Table 27 and are based on the operating
conditions set forth in Table 8, Table 11, and Table 13.
2.
These adjustments are used to convert output- and three-state-path times originally specified for the LVCMOS25 standard
with 12 mA drive and Fast slew rate to times that correspond to other signal standards. Do not adjust times that measure
when outputs go into a high-impedance state.
Table 26: Output Timing Adjustments for IOB (Cont’d)
Convert Output Time from LVCMOS25 with 12mA Drive and Fast
Slew Rate to the Following Signal Standard (IOSTANDARD)
Add the Adjustment Below
Units
Speed Grade: -4
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