參數(shù)資料
型號： XA3SD1800A-4FGG676I
廠商： Xilinx Inc
文件頁數(shù)： 34/58頁
文件大小： 0K
描述： SPARTAN-3ADSP FPGA 1800K 676FBGA
產(chǎn)品培訓(xùn)模塊： Extended Spartan 3A FPGA Family
標準包裝： 40
系列： Spartan®-3A DSP XA
LAB/CLB數(shù)： 4160
邏輯元件/單元數(shù)： 37440
RAM 位總計： 1548288
輸入/輸出數(shù)： 519
門數(shù)： 1800000
電源電壓： 1.14 V ~ 1.26 V
安裝類型： 表面貼裝
工作溫度： -40°C ~ 100°C
封裝/外殼： 676-BGA
供應(yīng)商設(shè)備封裝： 676-FBGA（27x27）
配用： 122-1574-ND - KIT DEVELOPMENT SPARTAN 3ADSP
XA Spartan-3A DSP Automotive FPGA Family Data Sheet
DS705 (v2.0) April 18, 2011
Product Specification
4
I/O Capabilities
The XA Spartan-3A DSP FPGA SelectIO interface supports many popular single-ended and differential standards. Table 2
shows the number of user I/Os as well as the number of differential I/O pairs available for each device/package combination.
Some of the user I/Os are unidirectional input-only pins as indicated in Table 2.
XA Spartan-3A DSP FPGAs support the following single-ended standards:
3.3V low-voltage TTL (LVTTL)
Low-voltage CMOS (LVCMOS) at 3.3V, 2.5V, 1.8V, 1.5V, or 1.2V
3.3V PCI at 33 MHz
HSTL I, II, and III at 1.5V and 1.8V, commonly used in memory applications
SSTL I and II at 1.8V, 2.5V, and 3.3V, commonly used for memory applications
XA Spartan-3A DSP FPGAs support the following differential standards:
LVDS, mini-LVDS, RSDS, and PPDS I/O at 2.5V or 3.3V
Bus LVDS I/O at 2.5V
TMDS I/O at 3.3V
Differential HSTL and SSTL I/O
LVPECL inputs at 2.5V or 3.3V
Production Status
Table 3 indicates the production status of each XA Spartan-3A DSP FPGA by temperature range and speed grade. The
table also lists the earliest speed file version required for creating a production configuration bitstream. Later versions are
also supported.
Table 2: Available User I/Os and Differential I/O Pairs
Device
CSG484
FGG676
User
Differential
User
Differential
XA3SD1800A
309
(60)
140
(78)
519
(110)
227
(131)
XA3SD3400A
309
(60)
140
(78)
469
(60)
213
(117)
Notes:
1.
The number shown in bold indicates the maximum number of I/O and input-only pins. The number shown in (italics) indicates the number
of input-only pins. The differential input-only pin count includes both differential pairs on input-only pins and differential pairs on I/O pins
within I/O banks that are restricted to differential inputs.
Table 3: XA Spartan-3A DSP FPGA Family Production Status (Production Speed File)
Temperature Range
I-Grade
Q-Grade
Speed Grade
Standard (-4)
Part Number
XA3SD1800A
Production (v1.32)
XA3SD3400A
Production (v1.32)
–
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XA3SD3400A 制造商:XILINX 制造商全稱:XILINX 功能描述:XA Spartan-3A DSP Automotive FPGA Family Data Sheet
XA3SD3400A-4CSG484I 功能描述:SPARTAN-3ADSP FPGA 3400K 484CSBG RoHS:是 類別:集成電路 (IC) >> 嵌入式 - FPGA（現(xiàn)場可編程門陣列） 系列:Spartan®-3A DSP XA 產(chǎn)品變化通告:Step Intro and Pkg Change 11/March/2008 標準包裝:1 系列:Virtex®-5 SXT LAB/CLB數(shù):4080 邏輯元件/單元數(shù):52224 RAM 位總計:4866048 輸入/輸出數(shù):480 門數(shù):- 電源電壓:0.95 V ~ 1.05 V 安裝類型:表面貼裝 工作溫度:-40°C ~ 100°C 封裝/外殼:1136-BBGA，F(xiàn)CBGA 供應(yīng)商設(shè)備封裝:1136-FCBGA 配用:568-5088-ND - BOARD DEMO DAC1408D750122-1796-ND - EVALUATION PLATFORM VIRTEX-5
XA3SD3400A-4FGG676I 功能描述:SPARTAN-3ADSP FPGA 3400K 676FBGA RoHS:是 類別:集成電路 (IC) >> 嵌入式 - FPGA（現(xiàn)場可編程門陣列） 系列:Spartan®-3A DSP XA 產(chǎn)品變化通告:Step Intro and Pkg Change 11/March/2008 標準包裝:1 系列:Virtex®-5 SXT LAB/CLB數(shù):4080 邏輯元件/單元數(shù):52224 RAM 位總計:4866048 輸入/輸出數(shù):480 門數(shù):- 電源電壓:0.95 V ~ 1.05 V 安裝類型:表面貼裝 工作溫度:-40°C ~ 100°C 封裝/外殼:1136-BBGA，F(xiàn)CBGA 供應(yīng)商設(shè)備封裝:1136-FCBGA 配用:568-5088-ND - BOARD DEMO DAC1408D750122-1796-ND - EVALUATION PLATFORM VIRTEX-5
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