參數(shù)資料
型號(hào): XA3SD1800A-4FGG676I
廠商: Xilinx Inc
文件頁(yè)數(shù): 35/58頁(yè)
文件大小: 0K
描述: SPARTAN-3ADSP FPGA 1800K 676FBGA
產(chǎn)品培訓(xùn)模塊: Extended Spartan 3A FPGA Family
標(biāo)準(zhǔn)包裝: 40
系列: Spartan®-3A DSP XA
LAB/CLB數(shù): 4160
邏輯元件/單元數(shù): 37440
RAM 位總計(jì): 1548288
輸入/輸出數(shù): 519
門數(shù): 1800000
電源電壓: 1.14 V ~ 1.26 V
安裝類型: 表面貼裝
工作溫度: -40°C ~ 100°C
封裝/外殼: 676-BGA
供應(yīng)商設(shè)備封裝: 676-FBGA(27x27)
配用: 122-1574-ND - KIT DEVELOPMENT SPARTAN 3ADSP
XA Spartan-3A DSP Automotive FPGA Family Data Sheet
DS705 (v2.0) April 18, 2011
Product Specification
40
DSP48A Timing
To reference the DSP48A block diagram, see the XtremeDSP DSP48A for Spartan-3A DSP FPGAs User Guide (UG431).
Table 35: Setup Times for the DSP48A
Symbol
Description
Pre-adder
Multiplier
Post-adder
Speed Grade: -4
Units
Min
Setup Times of Data/Control Pins to the Input Register Clock
TDSPDCK_AA
A input to A register CLK
–0.04
ns
TDSPDCK_DB
D input to B register CLK
Yes(1)
–1.88
ns
TDSPDCK_CC
C input to C register CLK
–0.05
ns
TDSPDCK_DD
D input to D register CLK
–0.04
ns
TDSPDCK_OPB
OPMODE input to B register CLK
Yes
–0.42
ns
TDSPDCK_OPOP
OPMODE input to OPMODE register CLK
–0.06
ns
Setup Times of Data Pins to the Pipeline Register Clock
TDSPDCK_AM
A input to M register CLK
–Yes
–3.79
ns
TDSPDCK_BM
B input to M register CLK
Yes
–4.97
ns
No
Yes
–3.79
ns
TDSPDCK_DM
D input to M register CLK
Yes
–5.06
ns
TDSPDCK_OPM
OPMODE to M register CLK
Yes
–5.42
ns
Setup Times of Data/Control Pins to the Output Register Clock
TDSPDCK_AP
A input to P register CLK
–Yes
Yes
5.49
ns
TDSPDCK_BP
B input to P register CLK
Yes
6.74
ns
No
Yes
5.48
ns
TDSPDCK_DP
D input to P register CLK
Yes
6.83
ns
TDSPDCK_CP
C input to P register CLK
Yes
2.18
ns
TDSPDCK_OPP
OPMODE input to P register CLK
Yes
7.18
ns
Notes:
1.
“Yes” means that the component is in the path. “No” means that the component is being bypassed. “–” means that no path exists, so it is not
applicable.
2.
The numbers in this table are based on the operating conditions set forth in Table 8.
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