參數(shù)資料
型號: XA3SD1800A-4FGG676I
廠商: Xilinx Inc
文件頁數(shù): 57/58頁
文件大?。?/td> 0K
描述: SPARTAN-3ADSP FPGA 1800K 676FBGA
產(chǎn)品培訓模塊: Extended Spartan 3A FPGA Family
標準包裝: 40
系列: Spartan®-3A DSP XA
LAB/CLB數(shù): 4160
邏輯元件/單元數(shù): 37440
RAM 位總計: 1548288
輸入/輸出數(shù): 519
門數(shù): 1800000
電源電壓: 1.14 V ~ 1.26 V
安裝類型: 表面貼裝
工作溫度: -40°C ~ 100°C
封裝/外殼: 676-BGA
供應(yīng)商設(shè)備封裝: 676-FBGA(27x27)
配用: 122-1574-ND - KIT DEVELOPMENT SPARTAN 3ADSP
XA Spartan-3A DSP Automotive FPGA Family Data Sheet
DS705 (v2.0) April 18, 2011
Product Specification
8
General Recommended Operating Conditions
Table 8: General Recommended Operating Conditions
Symbol
Description
Min
Nominal
Max
Units
TJ
Junction temperature
I-Grade
–40
–100
C
Q-Grade
–40
–125
C
VCCINT
Internal supply voltage
1.14
1.20
1.26
V
VCCO(1)
Output driver supply voltage
1.10
–3.60
V
VCCAUX
Auxiliary supply voltage(2)
VCCAUX = 2.5
2.25
2.50
2.75
V
VCCAUX = 3.3
3.00
3.30
3.60
V
Input voltage
PCI IOSTANDARD
–0.5
–VCCO+0.5
V
All other
IOSTANDARDs
IP or IO_#
–0.5
–4.10
V
–0.5
–4.10
V
TIN
Input signal transition time(5)
500
ns
Notes:
1.
This VCCO range spans the lowest and highest operating voltages for all supported I/O standards. Table 11 lists the recommended VCCO
range specific to each of the single-ended I/O standards, and Table 13 lists that specific to the differential standards.
2.
Define VCCAUX selection using CONFIG VCCAUX constraint.
3.
See XAPP459, Eliminating I/O Coupling Effects when Interfacing Large-Swing Single-Ended Signals to User I/O Pins on Spartan-3
Generation FPGAs.
4.
For single-ended signals that are placed on a differential-capable I/O, VIN of –0.2V to –0.5V is supported but can cause increased leakage
between the two pins. See Parasitic Leakage in UG331, Spartan-3 Generation FPGA User Guide.
5.
Measured between 10% and 90% VCCO. Follow Signal Integrity recommendations.
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