參數(shù)資料
型號(hào): XA3SD1800A-4FGG676I
廠商: Xilinx Inc
文件頁(yè)數(shù): 49/58頁(yè)
文件大?。?/td> 0K
描述: SPARTAN-3ADSP FPGA 1800K 676FBGA
產(chǎn)品培訓(xùn)模塊: Extended Spartan 3A FPGA Family
標(biāo)準(zhǔn)包裝: 40
系列: Spartan®-3A DSP XA
LAB/CLB數(shù): 4160
邏輯元件/單元數(shù): 37440
RAM 位總計(jì): 1548288
輸入/輸出數(shù): 519
門(mén)數(shù): 1800000
電源電壓: 1.14 V ~ 1.26 V
安裝類(lèi)型: 表面貼裝
工作溫度: -40°C ~ 100°C
封裝/外殼: 676-BGA
供應(yīng)商設(shè)備封裝: 676-FBGA(27x27)
配用: 122-1574-ND - KIT DEVELOPMENT SPARTAN 3ADSP
XA Spartan-3A DSP Automotive FPGA Family Data Sheet
DS705 (v2.0) April 18, 2011
Product Specification
53
Serial Peripheral Interface Configuration Timing
X-Ref Target - Figure 14
Figure 14: Waveforms for Serial Peripheral Interface Configuration
Table 53: Timing for Serial Peripheral Interface Configuration Mode
Symbol
Description
Minimum
Maximum
Units
TCCLK1
Initial CCLK clock period
TCCLKn
CCLK clock period after FPGA loads ConfigRate setting
TMINIT
Setup time on VS[2:0] variant-select pins and M[2:0] mode pins before the rising
edge of INIT_B
50
–ns
TINITM
Hold time on VS[2:0] variant-select pins and M[2:0] mode pins after the rising
edge of INIT_B
0
–ns
TCCO
MOSI output valid delay after CCLK falling edge
TDCC
Setup time on DIN data input before CCLK rising edge
TCCD
Hold time on DIN data input after CCLK rising edge
0
–ns
T
DH
T
DSU
Command
(msb)
T
V
T
CSS
<1:1:1>
INIT_B
M[2:0]
T
MINIT
T
INITM
DIN
CCLK
(Input)
T
CCLK
n
T
CCLK1
VS[2:0]
(Input)
New ConfigRate active
Mode input pins M[2:0] and variant select input pins VS[2:0] are sampled when INIT_B
goes High. After this point, input values do not matter until DONE goes High, at which
point these pins become user-I/O pins.
<0:0:1>
Pin initially pulled High by internal pull-up resistor if PUDC_B input is Low.
Pin initially high-impedance (Hi-Z) if PUDC_B input is High. External pull-up resistor required on CSO_B.
T
CCLK1
T
MCCL
n
T
MCCH
n
(Input)
Data
CSO_B
MOSI
T
CCO
T
MCCL1
T
MCCH1
T
DCC
T
CCD
(Input)
PROG_B
PUDC_B
(Input)
PUDC_B must be stable before INIT_B goes High and constant throughout the configuration process.
DS705_14_041311
(Open-Drain)
Shaded values indicate specifications on attached SPI Flash PROM.
Command
(msb-1)
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