參數資料
| 型號： | XA3SD3400A-4CSG484I |
| 廠商： | Xilinx Inc |
| 文件頁數： | 1/58頁 |
| 文件大?。?/td> | 0K |
| 描述： | SPARTAN-3ADSP FPGA 3400K 484CSBG |
| 產品培訓模塊： | Extended Spartan 3A FPGA Family |
| 標準包裝： | 84 |
| 系列： | Spartan®-3A DSP XA |
| LAB/CLB數： | 5968 |
| 邏輯元件/單元數： | 53712 |
| RAM 位總計： | 2322432 |
| 輸入/輸出數： | 309 |
| 門數： | 3400000 |
| 電源電壓： | 1.14 V ~ 1.26 V |
| 安裝類型： | 表面貼裝 |
| 工作溫度： | -40°C ~ 100°C |
| 封裝/外殼： | 484-FBGA，CSPBGA |
| 供應商設備封裝： | 484-CSPBGA |
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DS705 (v2.0) April 18, 2011
Product Specification
1
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United States and other countries. PCI, PCI Express, PCIe, and PCI-X are trademarks of PCI-SIG. All other trademarks are the property of their respective owners.
Summary
The Xilinx Automotive (XA) Spartan-3A DSP family of
FPGAs solves the design challenges in most high-volume,
cost-sensitive, high-performance DSP automotive
applications. The two-member family offers densities
ranging from 1.8 to 3.4 million system gates, as shown in
Introduction
XA devices are available in both extended-temperature
Q-Grade (–40°C to +125°C TJ) and I-Grade (–40°C to
+100°C TJ) and are qualified to the industry recognized
AEC-Q100 standard.
The XA Spartan-3A DSP family builds on the success of the
earlier XA Spartan-3E and XA Spartan-3 FPGA families by
adding hardened DSP MACs with pre-adders, significantly
increasing the throughput and performance of this low-cost
family. These XA Spartan-3A DSP family enhancements,
combined with proven 90 nm process technology, deliver
more functionality and bandwidth per dollar than ever
before, setting the new standard in the programmable logic
industry.
Because of their exceptionally low cost,
XA Spartan-3A DSP FPGAs are ideally suited to a wide
range of automotive electronics applications, including
infotainment, driver information, and driver assistance
modules.
The XA Spartan-3A DSP family is a superior alternative to
mask programmed ASICs. FPGAs avoid the high initial
mask set costs and lengthy development cycles, while also
permitting design upgrades in the field with no hardware
replacement necessary because of its inherent
programmability, an impossibility with conventional ASICs
and ASSPs with their inflexible architecture.
Features
Very low cost, high-performance DSP solution for
high-volume, cost-conscious applications
250 MHz DSP48A slices using XtremeDSP solution
Dedicated 18-bit by 18-bit multiplier
Available pipeline stages for enhanced performance of at
least 250 MHz in the standard -4 speed grade
48-bit accumulator for multiply-accumulate (MAC)
operation
Integrated adder for complex multiply or multiply-add
operation
Integrated 18-bit pre-adder
Optional cascaded Multiply or MAC
Dual-range VCCAUX supply simplifies 3.3V-only design
Suspend and Hibernate modes reduce system power
Multi-voltage, multi-standard SelectIO interface pins
Up to 519 I/O pins or 227 differential signal pairs
LVCMOS, LVTTL, HSTL, and SSTL single-ended I/O
3.3V, 2.5V, 1.8V, 1.5V, and 1.2V signaling
Selectable output drive, up to 24 mA per pin
QUIETIO standard reduces I/O switching noise
Full 3.3V ± 10% compatibility and hot-swap compliance
622+ Mb/s data transfer rate per differential I/O
LVDS, RSDS, mini-LVDS, HSTL/SSTL differential I/O
with integrated differential termination resistors
Enhanced Double Data Rate (DDR) support
DDR/DDR2 SDRAM support up to 266 Mb/s
Fully compliant 32-bit, 33 MHz PCI technology support
Abundant, flexible logic resources
Densities up to 53,712 logic cells, including optional shift
register
Efficient wide multiplexers, wide logic
Fast look-ahead carry logic
IEEE 1149.1/1532 JTAG programming/debug port
Hierarchical SelectRAM memory architecture
Up to 2,268 Kbits of fast block RAM with byte write
enables for processor applications
Up to 373 Kbits of efficient distributed RAM
Registered outputs on the block RAM with operation of at
least 280 MHz in the standard -4 speed grade
Eight Digital Clock Managers (DCMs)
Clock skew elimination (delay locked loop)
Frequency synthesis, multiplication, division
High-resolution phase shifting
Wide frequency range (5 MHz to over 320 MHz)
Eight low-skew global clock networks, eight additional
clocks per half device, plus abundant low-skew routing
Configuration interface to industry-standard PROMs
Low-cost, space-saving SPI serial Flash PROM
x8 or x8/x16 parallel NOR Flash PROM
Unique Device DNA identifier for design authentication
support plus Spartan-3A DSP FPGA Starter Kit
MicroBlaze and PicoBlaze embedded processor
cores
BGA packaging, Pb-free only
Common footprints support easy density migration
58
XA Spartan-3A DSP Automotive
FPGA Family Data Sheet
DS705 (v2.0) April 18, 2011
Product Specification
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| XA3SD3400A-4FGG676I | 功能描述:SPARTAN-3ADSP FPGA 3400K 676FBGA RoHS:是 類別:集成電路 (IC) >> 嵌入式 - FPGA（現場可編程門陣列） 系列:Spartan®-3A DSP XA 產品變化通告:Step Intro and Pkg Change 11/March/2008 標準包裝:1 系列:Virtex®-5 SXT LAB/CLB數:4080 邏輯元件/單元數:52224 RAM 位總計:4866048 輸入/輸出數:480 門數:- 電源電壓:0.95 V ~ 1.05 V 安裝類型:表面貼裝 工作溫度:-40°C ~ 100°C 封裝/外殼:1136-BBGA，FCBGA 供應商設備封裝:1136-FCBGA 配用:568-5088-ND - BOARD DEMO DAC1408D750122-1796-ND - EVALUATION PLATFORM VIRTEX-5 |
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