參數(shù)資料
型號： XA3SD3400A-4CSG484I
廠商： Xilinx Inc
文件頁數(shù)： 40/58頁
文件大?。?/td> 0K
描述： SPARTAN-3ADSP FPGA 3400K 484CSBG
產(chǎn)品培訓(xùn)模塊： Extended Spartan 3A FPGA Family
標(biāo)準(zhǔn)包裝： 84
系列： Spartan®-3A DSP XA
LAB/CLB數(shù)： 5968
邏輯元件/單元數(shù)： 53712
RAM 位總計： 2322432
輸入/輸出數(shù)： 309
門數(shù)： 3400000
電源電壓： 1.14 V ~ 1.26 V
安裝類型： 表面貼裝
工作溫度： -40°C ~ 100°C
封裝/外殼： 484-FBGA，CSPBGA
供應(yīng)商設(shè)備封裝： 484-CSPBGA
XA Spartan-3A DSP Automotive FPGA Family Data Sheet
DS705 (v2.0) April 18, 2011
Product Specification
45
Phase Shifter
Lock Time
LOCK_FX(2,3)
The time from deassertion at the DCM’s
Reset input to the rising transition at its
LOCKED output. The DFS asserts
LOCKED when the CLKFX and
CLKFX180 signals are valid. If using both
the DLL and the DFS, use the longer
locking time.
5MHz
F
CLKIN
15 MHz
All
–5
ms
FCLKIN
15 MHz
–
450
s
Notes:
1.
The numbers in this table are based on the operating conditions set forth in Table 8 and Table 39.
2.
DFS performance requires the additional logic automatically added by ISE 9.1i and later software revisions.
3.
For optimal jitter tolerance and faster lock time, use the CLKIN_PERIOD attribute.
4.
Maximum output jitter is characterized within a reasonable noise environment (40 SSOs and 25% CLB switching) on an FPGA. Output jitter
strongly depends on the environment, including the number of SSOs, the output drive strength, CLB utilization, CLB switching activities,
switching frequency, power supply and PCB design. The actual maximum output jitter depends on the system application.
5.
The CLKFX and CLKFX180 outputs always have an approximate 50% duty cycle.
6.
Some duty-cycle and alignment specifications include a percentage of the CLKFX output period. For example, the data sheet specifies a
maximum CLKFX jitter of “±[1% of CLKFX period + 200]”. Assume the CLKFX output frequency is 100 MHz. The equivalent CLKFX period
is 10 ns and 1% of 10 ns is 0.1 ns or 100 ps. According to the data sheet, the maximum jitter is ±[100 ps + 200 ps] = ±300 ps.
Table 41: Recommended Operating Conditions for the PS in Variable Phase Mode
Symbol
Description
Speed Grade: -4
Units
Min
Max
Operating Frequency Ranges
PSCLK_FREQ (FPSCLK)
Frequency for the PSCLK input
1
167
MHz
Input Pulse Requirements
PSCLK_PULSE
PSCLK pulse width as a percentage of the PSCLK period
40%
60%
–
Table 42: Switching Characteristics for the PS in Variable Phase Mode
Symbol
Description
Phase Shift Amount
Units
Phase Shifting Range
Maximum allowed number of
DCM_DELAY_STEP(3) steps for a
given CLKIN clock period, where
T = CLKIN clock period in ns. If using
CLKIN_DIVIDE_BY_2 = TRUE,
double the clock effective clock
period.
CLKIN
60 MHz
[INTEGER(10 (T
CLKIN – 3 ns))]
steps
CLKIN
60 MHz [INTEGER(15 (T
CLKIN – 3 ns))]
FINE_SHIFT_RANGE_MIN
Minimum guaranteed delay for variable phase shifting
[MAX_STEPS
DCM_DELAY_STEP_MIN]
ns
FINE_SHIFT_RANGE_MA
X
Maximum guaranteed delay for variable phase shifting
[MAX_STEPS
DCM_DELAY_STEP_MAX]
ns
Notes:
1.
The numbers in this table are based on the operating conditions set forth in Table 8 and Table 41.
2.
The maximum variable phase shift range, MAX_STEPS, is only valid when the DCM is has no initial fixed phase shifting, that is, the
PHASE_SHIFT attribute is set to 0.
3.
The DCM_DELAY_STEP values are provided at the bottom of Table 38.
Table 40: Switching Characteristics for the DFS (Cont’d)
Symbol
Description
Device
Speed Grade: -4
Units
Min
Max
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