參數(shù)資料
型號(hào): XA3SD3400A-4CSG484I
廠商: Xilinx Inc
文件頁數(shù): 52/58頁
文件大?。?/td> 0K
描述: SPARTAN-3ADSP FPGA 3400K 484CSBG
產(chǎn)品培訓(xùn)模塊: Extended Spartan 3A FPGA Family
標(biāo)準(zhǔn)包裝: 84
系列: Spartan®-3A DSP XA
LAB/CLB數(shù): 5968
邏輯元件/單元數(shù): 53712
RAM 位總計(jì): 2322432
輸入/輸出數(shù): 309
門數(shù): 3400000
電源電壓: 1.14 V ~ 1.26 V
安裝類型: 表面貼裝
工作溫度: -40°C ~ 100°C
封裝/外殼: 484-FBGA,CSPBGA
供應(yīng)商設(shè)備封裝: 484-CSPBGA
XA Spartan-3A DSP Automotive FPGA Family Data Sheet
DS705 (v2.0) April 18, 2011
Product Specification
56
Table 56: Configuration Timing Requirements for Attached Parallel NOR Flash)
Symbol
Description
Requirement
Units
TCE
(tELQV)
Parallel NOR Flash PROM chip-select time
ns
TOE
(tGLQV)
Parallel NOR Flash PROM output-enable time
ns
TACC
(tAVQV)
Parallel NOR Flash PROM read access time
ns
TBYTE
(tFLQV, tFHQV)
For x8/x16 PROMs only: BYTE# to output valid time(3)
ns
Notes:
1.
These requirements are for successful FPGA configuration in BPI mode, where the FPGA generates the CCLK signal. The
post-configuration timing can be different to support the specific needs of the application loaded into the FPGA.
2.
Subtract additional printed circuit board routing delay as required by the application.
3.
The initial BYTE# timing can be extended using an external, appropriately sized pull-down resistor on the FPGA’s LDC2 pin. The resistor
value also depends on whether the FPGA’s PUDC_B pin is High or Low.
T
CE
T
INITADDR
T
OE
T
INITADDR
T
ACC
50%T
CCLKn min
T
CCO
T
DCC
PCB
T
BYTE
T
INITADDR
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