參數(shù)資料
型號： XA3SD3400A-4CSG484I
廠商： Xilinx Inc
文件頁數(shù)： 25/58頁
文件大?。?/td> 0K
描述： SPARTAN-3ADSP FPGA 3400K 484CSBG
產(chǎn)品培訓(xùn)模塊： Extended Spartan 3A FPGA Family
標(biāo)準(zhǔn)包裝： 84
系列： Spartan®-3A DSP XA
LAB/CLB數(shù)： 5968
邏輯元件/單元數(shù)： 53712
RAM 位總計： 2322432
輸入/輸出數(shù)： 309
門數(shù)： 3400000
電源電壓： 1.14 V ~ 1.26 V
安裝類型： 表面貼裝
工作溫度： -40°C ~ 100°C
封裝/外殼： 484-FBGA，CSPBGA
供應(yīng)商設(shè)備封裝： 484-CSPBGA
XA Spartan-3A DSP Automotive FPGA Family Data Sheet
DS705 (v2.0) April 18, 2011
Product Specification
31
Using IBIS Models to Simulate Load Conditions in Application
IBIS models permit the most accurate prediction of timing delays for a given application. The parameters found in the IBIS
model (VREF, RREF, and VMEAS) correspond directly with the parameters used in Table 27 (VT, RT, and VM). Do not confuse
VREF (the termination voltage) from the IBIS model with VREF (the input-switching threshold) from the table. A fourth
parameter, CREF, is always zero. The four parameters describe all relevant output test conditions. IBIS models are found in
the Xilinx development software as well as at the following link:
Delays for a given application are simulated according to its specific load conditions as follows:
1.
Simulate the desired signal standard with the output driver connected to the test setup shown in Figure 9. Use
parameter values VT, RT, and VM from Table 27. CREF is zero.
2.
Record the time to VM.
3.
Simulate the same signal standard with the output driver connected to the PCB trace with load. Use the appropriate IBIS
model (including VREF, RREF, CREF, and VMEAS values) or capacitive value to represent the load.
4.
Record the time to VMEAS.
5.
Compare the results of steps 2 and 4. Add (or subtract) the increase (or decrease) in delay to (or from) the appropriate
Output standard adjustment (Table 26) to yield the worst-case delay of the PCB trace.
Simultaneously Switching Output Guidelines
This section provides guidelines for the recommended maximum allowable number of Simultaneous Switching Outputs
(SSOs). These guidelines describe the maximum number of user I/O pins of a given output signal standard that should
simultaneously switch in the same direction, while maintaining a safe level of switching noise. Meeting these guidelines for
the stated test conditions ensures that the FPGA operates free from the adverse effects of ground and power bounce.
Ground or power bounce occurs when a large number of outputs simultaneously switch in the same direction. The output
drive transistors all conduct current to a common voltage rail. Low-to-High transitions conduct to the VCCO rail; High-to-Low
transitions conduct to the GND rail. The resulting cumulative current transient induces a voltage difference across the
inductance that exists between the die pad and the power supply or ground return. The inductance is associated with
bonding wires, the package lead frame, and any other signal routing inside the package. Other variables contribute to SSO
noise levels, including stray inductance on the PCB as well as capacitive loading at receivers. Any SSO-induced voltage
consequently affects internal switching noise margins and ultimately signal quality.
Table 28 and Table 29 provide the essential SSO guidelines. For each device/package combination, Table 28 provides the
number of equivalent VCCO/GND pairs. The equivalent number of pairs is based on characterization and may not match the
physical number of pairs. For each output signal standard and drive strength, Table 29 recommends the maximum number
of SSOs, switching in the same direction, allowed per VCCO/GND pair within an I/O bank. The guidelines in Table 29 are
categorized by package style, slew rate, and output drive current. Furthermore, the number of SSOs is specified by I/O bank.
Generally, the left and right I/O banks (Banks 1 and 3) support higher output drive current.
Multiply the appropriate numbers from Table 28 and Table 29 to calculate the maximum number of SSOs allowed within an
I/O bank. Exceeding these SSO guidelines might result in increased power or ground bounce, degraded signal integrity, or
increased system jitter.
SSOMAX/IO Bank = Table 28 x Table 29
The recommended maximum SSO values assumes that the FPGA is soldered on the printed circuit board and that the board
uses sound design practices. The SSO values do not apply for FPGAs mounted in sockets, due to the lead inductance
introduced by the socket.
The SSO values assume that the VCCAUX is powered at 3.3V. Setting VCCAUX to 2.5V provides better SSO characteristics.
Table 28: Equivalent VCCO/GND Pairs per Bank
Device
Package Style (Pb-free)
CSG484
FGG676
XA3SD1800A
6
9
XA3SD3400A
6
10
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