參數(shù)資料
型號(hào)： XA3SD3400A-4CSG484I
廠商： Xilinx Inc
文件頁數(shù)： 32/58頁
文件大?。?/td> 0K
描述： SPARTAN-3ADSP FPGA 3400K 484CSBG
產(chǎn)品培訓(xùn)模塊： Extended Spartan 3A FPGA Family
標(biāo)準(zhǔn)包裝： 84
系列： Spartan®-3A DSP XA
LAB/CLB數(shù)： 5968
邏輯元件/單元數(shù)： 53712
RAM 位總計(jì)： 2322432
輸入/輸出數(shù)： 309
門數(shù)： 3400000
電源電壓： 1.14 V ~ 1.26 V
安裝類型： 表面貼裝
工作溫度： -40°C ~ 100°C
封裝/外殼： 484-FBGA，CSPBGA
供應(yīng)商設(shè)備封裝： 484-CSPBGA
XA Spartan-3A DSP Automotive FPGA Family Data Sheet
DS705 (v2.0) April 18, 2011
Product Specification
38
Clock Buffer/Multiplexer Switching Characteristics
Table 31: CLB Distributed RAM Switching Characteristics
Symbol
Description
Speed Grade: -4
Units
Min
Max
Clock-to-Output Times
TSHCKO
Time from the active edge at the CLK input to data appearing on the
distributed RAM output
–1.72
ns
Setup Times
TDS
Setup time of data at the BX or BY input before the active transition at the CLK
input of the distributed RAM
–0.02
–ns
TAS
Setup time of the F/G address inputs before the active transition at the CLK
input of the distributed RAM
0.36
–ns
TWS
Setup time of the write enable input before the active transition at the CLK
input of the distributed RAM
0.59
–ns
Hold Times
TDH
Hold time of the BX and BY data inputs after the active transition at the CLK
input of the distributed RAM
0.13
–ns
TAH, TWH
Hold time of the F/G address inputs or the write enable input after the active
transition at the CLK input of the distributed RAM
0.01
–ns
Clock Pulse Width
TWPH, TWPL
Minimum High or Low pulse width at CLK input
1.01
–ns
Table 32: CLB Shift Register Switching Characteristics
Symbol
Description
Speed Grade: -4
Units
Min
Max
Clock-to-Output Times
TREG
Time from the active edge at the CLK input to data appearing on the shift
register output
–4.82
ns
Setup Times
TSRLDS
Setup time of data at the BX or BY input before the active transition at the CLK
input of the shift register
0.18
–ns
Hold Times
TSRLDH
Hold time of the BX or BY data input after the active transition at the CLK input
of the shift register
0.16
–ns
Clock Pulse Width
TWPH, TWPL
Minimum High or Low pulse width at CLK input
1.01
–ns
Table 33: Clock Distribution Switching Characteristics
Description
Symbol
Minimum
Maximum
Units
Global clock buffer (BUFG, BUFGMUX, BUFGCE) I input to O-output delay
TGIO
–0.23
ns
Global clock multiplexer (BUFGMUX) select S-input setup to I0 and I1 inputs.
Same as BUFGCE enable CE-input
TGSI
–0.63
ns
Frequency of signals distributed on global buffers (all sides)
FBUFG
0
334
MHz
Notes:
1.
The numbers in this table are based on the operating conditions set forth in Table 8.
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