- 您現(xiàn)在的位置：買賣IC網 > PDF目錄19312 > XC3S50-4TQG144I (Xilinx Inc)SPARTAN-3 FPGA 50K STD 144-TQFP PDF資料下載
參數資料
| 型號： | XC3S50-4TQG144I |
| 廠商： | Xilinx Inc |
| 文件頁數： | 124/272頁 |
| 文件大小： | 0K |
| 描述： | SPARTAN-3 FPGA 50K STD 144-TQFP |
| 產品培訓模塊： | Extended Spartan 3A FPGA Family |
| 標準包裝： | 60 |
| 系列： | Spartan®-3 |
| LAB/CLB數： | 192 |
| 邏輯元件/單元數： | 1728 |
| RAM 位總計： | 73728 |
| 輸入/輸出數： | 97 |
| 門數： | 50000 |
| 電源電壓： | 1.14 V ~ 1.26 V |
| 安裝類型： | 表面貼裝 |
| 工作溫度： | -40°C ~ 100°C |
| 封裝/外殼： | 144-LQFP |
| 供應商設備封裝： | 144-TQFP（20x20） |
| 其它名稱： | 122-1720 XC3S50-4TQG144I-ND |
第1頁第2頁第3頁第4頁第5頁第6頁第7頁第8頁第9頁第10頁第11頁第12頁第13頁第14頁第15頁第16頁第17頁第18頁第19頁第20頁第21頁第22頁第23頁第24頁第25頁第26頁第27頁第28頁第29頁第30頁第31頁第32頁第33頁第34頁第35頁第36頁第37頁第38頁第39頁第40頁第41頁第42頁第43頁第44頁第45頁第46頁第47頁第48頁第49頁第50頁第51頁第52頁第53頁第54頁第55頁第56頁第57頁第58頁第59頁第60頁第61頁第62頁第63頁第64頁第65頁第66頁第67頁第68頁第69頁第70頁第71頁第72頁第73頁第74頁第75頁第76頁第77頁第78頁第79頁第80頁第81頁第82頁第83頁第84頁第85頁第86頁第87頁第88頁第89頁第90頁第91頁第92頁第93頁第94頁第95頁第96頁第97頁第98頁第99頁第100頁第101頁第102頁第103頁第104頁第105頁第106頁第107頁第108頁第109頁第110頁第111頁第112頁第113頁第114頁第115頁第116頁第117頁第118頁第119頁第120頁第121頁第122頁第123頁當前第124頁第125頁第126頁第127頁第128頁第129頁第130頁第131頁第132頁第133頁第134頁第135頁第136頁第137頁第138頁第139頁第140頁第141頁第142頁第143頁第144頁第145頁第146頁第147頁第148頁第149頁第150頁第151頁第152頁第153頁第154頁第155頁第156頁第157頁第158頁第159頁第160頁第161頁第162頁第163頁第164頁第165頁第166頁第167頁第168頁第169頁第170頁第171頁第172頁第173頁第174頁第175頁第176頁第177頁第178頁第179頁第180頁第181頁第182頁第183頁第184頁第185頁第186頁第187頁第188頁第189頁第190頁第191頁第192頁第193頁第194頁第195頁第196頁第197頁第198頁第199頁第200頁第201頁第202頁第203頁第204頁第205頁第206頁第207頁第208頁第209頁第210頁第211頁第212頁第213頁第214頁第215頁第216頁第217頁第218頁第219頁第220頁第221頁第222頁第223頁第224頁第225頁第226頁第227頁第228頁第229頁第230頁第231頁第232頁第233頁第234頁第235頁第236頁第237頁第238頁第239頁第240頁第241頁第242頁第243頁第244頁第245頁第246頁第247頁第248頁第249頁第250頁第251頁第252頁第253頁第254頁第255頁第256頁第257頁第258頁第259頁第260頁第261頁第262頁第263頁第264頁第265頁第266頁第267頁第268頁第269頁第270頁第271頁第272頁
Spartan-3 FPGA Family: Functional Description
DS099 (v3.1) June 27, 2013
Product Specification
21
Supply Voltages for the IOBs
Three different supplies power the IOBs:
The VCCO supplies, one for each of the FPGA’s I/O banks, power the output drivers, except when using the GTL and
GTLP signal standards. The voltage on the VCCO pins determines the voltage swing of the output signal.
VCCINT is the main power supply for the FPGA’s internal logic.
The VCCAUX is an auxiliary source of power, primarily to optimize the performance of various FPGA functions such as
I/O switching.
The I/Os During Power-On, Configuration, and User Mode
With no power applied to the FPGA, all I/Os are in a high-impedance state. The VCCINT (1.2V), VCCAUX (2.5V), and VCCO
supplies may be applied in any order. Before power-on can finish, VCCINT, VCCO Bank 4, and VCCAUX must have reached
their respective minimum recommended operating levels (see Table 29, page 59). At this time, all I/O drivers also will be in
a high-impedance state. VCCO Bank 4, VCCINT, and VCCAUX serve as inputs to the internal Power-On Reset circuit (POR).
A Low level applied to the HSWAP_EN input enables pull-up resistors on User I/Os from power-on throughout configuration.
A High level on HSWAP_EN disables the pull-up resistors, allowing the I/Os to float. If the HSWAP_EN pin is floating, then
an internal pull-up resistor pulls HSWAP_EN High. As soon as power is applied, the FPGA begins initializing its
configuration memory. At the same time, the FPGA internally asserts the Global Set-Reset (GSR), which asynchronously
resets all IOB storage elements to a Low state.
Upon the completion of initialization, INIT_B goes High, sampling the M0, M1, and M2 inputs to determine the configuration
mode. At this point, the configuration data is loaded into the FPGA. The I/O drivers remain in a high-impedance state (with
or without pull-up resistors, as determined by the HSWAP_EN input) throughout configuration.
The Global Three State (GTS) net is released during Start-Up, marking the end of configuration and the beginning of design
operation in the User mode. At this point, those I/Os to which signals have been assigned go active while all unused I/Os
remain in a high-impedance state. The release of the GSR net, also part of Start-up, leaves the IOB registers in a Low state
by default, unless the loaded design reverses the polarity of their respective RS inputs.
In User mode, all internal pull-up resistors on the I/Os are disabled and HSWAP_EN becomes a “don’t care” input. If it is
desirable to have pull-up or pull-down resistors on I/Os carrying signals, the appropriate symbol—e.g., PULLUP,
PULLDOWN—must be placed at the appropriate pads in the design. The Bitstream Generator (Bitgen) option UnusedPin
available in the Xilinx development software determines whether unused I/Os collectively have pull-up resistors, pull-down
resistors, or no resistors in User mode.
CLB Overview
For more details on the CLBs, refer to the chapter entitled “Using Configurable Logic Blocks” in UG331.
The Configurable Logic Blocks (CLBs) constitute the main logic resource for implementing synchronous as well as
combinatorial circuits. Each CLB comprises four interconnected slices, as shown in Figure 11. These slices are grouped in
pairs. Each pair is organized as a column with an independent carry chain.
The nomenclature that the FPGA Editor—part of the Xilinx development software—uses to designate slices is as follows:
The letter ‘X’ followed by a number identifies columns of slices. The ‘X’ number counts up in sequence from the left side of
the die to the right. The letter ‘Y’ followed by a number identifies the position of each slice in a pair as well as indicating the
CLB row. The ‘Y’ number counts slices starting from the bottom of the die according to the sequence: 0, 1, 0, 1 (the first CLB
row); 2, 3, 2, 3 (the second CLB row); etc. Figure 11 shows the CLB located in the lower left-hand corner of the die. Slices
X0Y0 and X0Y1 make up the column-pair on the left where as slices X1Y0 and X1Y1 make up the column-pair on the right.
For each CLB, the term “l(fā)eft-hand” (or SLICEM) indicates the pair of slices labeled with an even ‘X’ number, such as X0, and
the term “right-hand” (or SLICEL) designates the pair of slices with an odd ‘X’ number, e.g., X1.
相關PDF資料 |
PDF描述 |
|---|---|
| VE-21L-EU | CONVERTER MOD DC/DC 28V 200W |
| GBM08DCMS | CONN EDGECARD 16POS .156 WW |
| TAP336M025CRW | CAP TANT 33UF 25V 20% RADIAL |
| VE-212-EU | CONVERTER MOD DC/DC 15V 200W |
| EP4S100G5H40I2N | IC STRATIX IV GT 530K 1517HBGA |
相關代理商/技術參數 |
參數描述 |
|---|---|
| XC3S50-4VQ100C | 制造商:Xilinx 功能描述:FPGA SPARTAN-3 50K GATES 1728 CELLS 630MHZ 1.2V 100VTQFP - Trays |
| XC3S50-4VQ100I | 制造商:Xilinx 功能描述:FPGA SPARTAN-3 50K GATES 1728 CELLS 630MHZ 1.2V 100VTQFP - Trays |
| XC3S50-4VQG100C | 功能描述:IC SPARTAN-3 FPGA 50K 100VTQFP RoHS:是 類別:集成電路 (IC) >> 嵌入式 - FPGA（現(xiàn)場可編程門陣列） 系列:Spartan®-3 標準包裝:60 系列:XP LAB/CLB數:- 邏輯元件/單元數:10000 RAM 位總計:221184 輸入/輸出數:244 門數:- 電源電壓:1.71 V ~ 3.465 V 安裝類型:表面貼裝 工作溫度:0°C ~ 85°C 封裝/外殼:388-BBGA 供應商設備封裝:388-FPBGA（23x23） 其它名稱:220-1241 |
| XC3S50-4VQG100I | 功能描述:SPARTAN-3A FPGA 50K STD 100-VQFP RoHS:是 類別:集成電路 (IC) >> 嵌入式 - FPGA（現(xiàn)場可編程門陣列） 系列:Spartan®-3 標準包裝:40 系列:Spartan® 6 LX LAB/CLB數:3411 邏輯元件/單元數:43661 RAM 位總計:2138112 輸入/輸出數:358 門數:- 電源電壓:1.14 V ~ 1.26 V 安裝類型:表面貼裝 工作溫度:-40°C ~ 100°C 封裝/外殼:676-BGA 供應商設備封裝:676-FBGA（27x27） |
| XC3S50-4VQG100I4022 | 制造商:Xilinx 功能描述: |
發(fā)布緊急采購，3分鐘左右您將得到回復。