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參數(shù)資料
型號： XE8801AMI027LF
廠商： Semtech
文件頁數(shù)： 18/135頁
文件大小： 0K
描述： IC DAS 16BIT FLASH 8K MTP 44LQFP
標(biāo)準(zhǔn)包裝： 800
系列： XE880x
應(yīng)用： 感測機(jī)
核心處理器： Coolrisc816?
程序存儲器類型： 閃存（22 kB）
控制器系列： XE8000
RAM 容量： 512 x 8
接口： UART，USRT
輸入/輸出數(shù)： 24
電源電壓： 2.4 V ~ 5.5 V
工作溫度： -40°C ~ 85°C
安裝類型： 表面貼裝
封裝/外殼： 44-VFQFN 裸露焊盤
包裝： 托盤
供應(yīng)商設(shè)備封裝： 44-MLPQ（7x7）
產(chǎn)品目錄頁面： 585 (CN2011-ZH PDF)
配用： XE8000MP-ND - PROG BOARD AND PROSTART2 CARD
Semtech 2005
www.semtech.com
16-29
XE8801A – SX8801R
Supply
GAIN = 1
GAIN =5
GAIN = 10
GAIN = 20
GAIN =100
Unit
VDD = 5V
79
78
100
99
97
dB
VDD = 3V
72
79
90
86
dB
Table 16-29 PSRR (n = 16 bits, VIN = VREF = 2.5V, fS = 500kHz)
16.9
Application Hints
16.9.1
Input Impedance
The PGAs of the acquisition chain employ switched-capacitor techniques. For this reason, while a conversion is
done, the input impedance on the selected channel of the PGAs is inversely proportional to the sampling frequency
fS and to stage gain as given in equation 22.
gain
f
Hz
Z
s
in
≥
9
10
768
(Eq. 22)
The input impedance observed is the input impedance of the first PGA stage that is enabled or the input impedance
of the ADC if all three stages are disabled.
PGA1 (with a gain of 10), PGA2 (with a gain of 10) and PGA3 (with a gain of 10) each have a minimum input
impedance of 150k
at f
S = 512kHz (see Specification Table). Larger input impedance can be obtained by reducing
the gain and/or by reducing the sampling frequency. Therefor, with a gain of 1 and a sampling frequency of 100kHz,
Zin > 7.6M.
The input impedance on channels that are not selected is very high (>100M
).
16.9.2
PGA Settling or Input Channel Modifications
PGAs are reset after each writing operation to registers RegAcCfg1-5. Similarly, input channels are switched after
modifications of AMUX[4:0] or VMUX. To ensure precise conversion, the ADC must be started after a PGA or inputs
common-mode stabilization delay. This is done by writing bit START several cycles after PGA settings modification or
channel switching. Delay between PGA start or input channel switching and ADC start should be equivalent to OSR
(between 8 and 1024) number of cycles. This delay does not apply to conversions made without the PGAs.
If the ADC is not settled within the specified period, there is most probably an input impedance problem (see
previous section).
16.9.3
PGA Gain & Offset, Linearity and Noise
Hereafter are a few design guidelines that should be taken into account when using the ZoomingADC
:
1)
Keep in mind that increasing the overall PGA gain, or "zooming" coefficient, improves linearity but degrades
noise performance.
2)
Use the minimum number of PGA stages necessary to produce the desired gain ("zooming") and offset.
Bypass unnecessary PGAs.
3)
For high gains (>50), use PGA stage 1. For low gains (<50) use stages 2 and 3.
4)
For the lowest noise, set the highest possible gain on the first (front) PGA stage used in the chain. For
example, in an application where a gain of 20 is needed, set the gain of PGA2 to 10, set the gain of PGA3
to 2.
Not
Recommended
for
New
Designs
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