參數(shù)資料
型號： XE8801AMI027LF
廠商： Semtech
文件頁數(shù)： 67/135頁
文件大?。?/td> 0K
描述： IC DAS 16BIT FLASH 8K MTP 44LQFP
標(biāo)準(zhǔn)包裝： 800
系列： XE880x
應(yīng)用： 感測機(jī)
核心處理器： Coolrisc816?
程序存儲器類型： 閃存（22 kB）
控制器系列： XE8000
RAM 容量： 512 x 8
接口： UART，USRT
輸入/輸出數(shù)： 24
電源電壓： 2.4 V ~ 5.5 V
工作溫度： -40°C ~ 85°C
安裝類型： 表面貼裝
封裝/外殼： 44-VFQFN 裸露焊盤
包裝： 托盤
供應(yīng)商設(shè)備封裝： 44-MLPQ（7x7）
產(chǎn)品目錄頁面： 585 (CN2011-ZH PDF)
配用： XE8000MP-ND - PROG BOARD AND PROSTART2 CARD
Semtech 2005
www.semtech.com
6-3
XE8801A – SX8801R
Pos.
RegSysWD
Rw
Reset
Function
7 – 4
-
r
0000
unused
WDKey[3]
w
Watchdog Key bit 3
3
WDCounter[3]
r
0 resetcold
Watchdog counter bit 3
WDKey[2]
w
Watchdog Key bit 2
2
WDCounter[2]
r
0 resetcold
Watchdog counter bit 2
WDKey[1]
w
Watchdog Key bit 1
1
WDCounter[1]
r
0 resetcold
Watchdog counter bit 1
WDKey[0]
w
Watchdog Key bit 0
0
WDCounter[0]
r
0 resetcold
Watchdog counter bit 0
Table 6-3. RegSysWD register
6.4
Reset handling capabilities
There are 5 reset sources:
Power On Reset (POR)
External reset from the RESET pin
Programmable Port A input combination
Programmable watchdog timer reset
Programmable BusError reset on processor access outside the allocated memory map
Another reset source is the bit Sleep in the RegSysReset register. This source is fully controlled by software and
is only used during the sleep mode.
Four internal reset signals are generated from these sources and distributed through the system:
resetcold:
is asserted on POR
resetsystem: is asserted when resetcold or any other enabled reset source is active
resetpconf:
is asserted when resetsystem is active and if the EnResPConf bit in the RegSysCtrl register
is set. This reset is generally used in the different ports. It allows to maintain the port
configuration unchanged while the rest of the circuit is reset.
resetsleep:
is asserted when the circuit is in sleep mode
For the circuits XE8801AM/XE88LC01AM/SX8801R and XE8805AM/XE88LC05AM
(2) For the circuits XE88LC01 and XE88LC05
Table 6-4 shows a summary of the dependency of the internal reset signals on the various reset sources. In all the
tables describing the different registers, the reset source is indicated.
Internal reset signals
resetpconf
Asserted
reset source
resetsystem
when
EnResPConf=0
when
EnResPConf=1
resetsleep
resetcold
POR
Asserted
RESET pin (1)
Asserted
RESET pin (2)
Asserted
-
Asserted
-
PortA input
Asserted
-
Asserted
-
Watchdog
Asserted
-
Asserted
-
BusError
Asserted
-
Asserted
-
Sleep
-
Asserted
-
(1) For the circuits XE8801AM/XE88LC01AM/SX8801R and XE8805AM/XE88LC05AM
(2) For the circuits XE88LC01 and XE88LC05
Table 6-4 Internal reset assertion as a function of the reset source.
Not
Recommended
for
New
Designs
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