參數(shù)資料
型號： XE8801AMI027LF
廠商： Semtech
文件頁數(shù)： 99/135頁
文件大?。?/td> 0K
描述： IC DAS 16BIT FLASH 8K MTP 44LQFP
標準包裝： 800
系列： XE880x
應用： 感測機
核心處理器： Coolrisc816?
程序存儲器類型： 閃存（22 kB）
控制器系列： XE8000
RAM 容量： 512 x 8
接口： UART，USRT
輸入/輸出數(shù)： 24
電源電壓： 2.4 V ~ 5.5 V
工作溫度： -40°C ~ 85°C
安裝類型： 表面貼裝
封裝/外殼： 44-VFQFN 裸露焊盤
包裝： 托盤
供應商設備封裝： 44-MLPQ（7x7）
產品目錄頁面： 585 (CN2011-ZH PDF)
配用： XE8000MP-ND - PROG BOARD AND PROSTART2 CARD
Semtech 2005
www.semtech.com
12-3
XE8801A – SX8801R
Pos.
RegPBAna
rw
reset
description in digital mode
description in analog mode
7 – 4
--
r
0000
Unused
3
PBAna [3]
r w
0 resetpconf
Set PB[7:6] in analog mode
2
PBAna [2]
r w
0 resetpconf
Set PB[5:4] in analog mode
1
PBAna [1]
r w
0 resetpconf
Set PB[3:2] in analog mode
0
PBAna [0]
r w
0 resetpconf
Set PB[1:0] in analog mode
Table 12-6: RegPBAna
Note: Depending on the status of the EnResPConf bit in RegSysCtrl, the reset conditions of the registers are
different. See the reset block documentation for more details on the resetpconf signal.
12.4 Port B capabilities
Port B
usage (priority)
name
analog
(high)
functions
(medium)
digital
(low) (default)
PB[7]
uart Rx
I/O
PB[6]
analog
uart Tx
I/O
PB[5]
usrt S1
I/O
PB[4]
analog
usrt S0
I/O
PB[3]
32 kHz
I/O
PB[2]
analog
clock CPU
I/O
PB[1]
PWM1 Counter C (C+D)
I/O
PB[0]
analog
PWM0 Counter A (A+B)
I/O
Table 12-7: Different Port B functionality
Table 12-7 shows the different usage that can be made of Port B with the order of priority. If a pair of pins is
selected to be analog, it overwrites the function and digital set-up. If the pin is not selected as analog, but a
function is enabled, it overwrites the digital set-up. If neither the analog nor function are selected for a pin, it is used
as an ordinary digital I/O. This is the default configuration at start-up.
12.5 Port B analog capability
12.5.1
Port B analog configuration
Port B terminals can be attached to a 4 line analog bus by setting the PBAna[x] bits to 1 in the RegPBAna
register.
The other registers then define the connection of these 4 analog lines to the different pads of Port B. This can be
used to implement a simple LCD driver or A/D converter. Analog switching is available only when the circuit is
powered with sufficient voltage (see specification below). Below the specified supply voltage, only voltages that are
close to VSS or VBAT can be switched.
When PBAna[x] is set to 1, a pair of Port B terminals is switched from digital I/O mode to analog mode. The usage
of the registers RegPBPullup, RegPBOut and RegPBDir define the analog configuration (see Table 12-8).
When PBAna[x] = 1, then PBPullup[x] connects the pin to the analog bus. PBDir[x] and PBPOut[x] select which
of the 4 analog lines is used. For odd values of x, the selection bits are in the register RegPBOut (see Table 12-8).
For even values of x, the selection bits are in the register RegPBDir (see Table 12-9).
Not
Recommended
for
New
Designs
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