參數(shù)資料
型號： XE8801AMI027LF
廠商： Semtech
文件頁數(shù)： 84/135頁
文件大?。?/td> 0K
描述： IC DAS 16BIT FLASH 8K MTP 44LQFP
標(biāo)準(zhǔn)包裝： 800
系列： XE880x
應(yīng)用： 感測機(jī)
核心處理器： Coolrisc816?
程序存儲器類型： 閃存（22 kB）
控制器系列： XE8000
RAM 容量： 512 x 8
接口： UART，USRT
輸入/輸出數(shù)： 24
電源電壓： 2.4 V ~ 5.5 V
工作溫度： -40°C ~ 85°C
安裝類型： 表面貼裝
封裝/外殼： 44-VFQFN 裸露焊盤
包裝： 托盤
供應(yīng)商設(shè)備封裝： 44-MLPQ（7x7）
產(chǎn)品目錄頁面： 585 (CN2011-ZH PDF)
配用： XE8000MP-ND - PROG BOARD AND PROSTART2 CARD
Semtech 2005
www.semtech.com
8-3
XE8801A – SX8801R
pos.
RegIrqMid
rw
reset
function
7
RegIrqMid[7]
r
c1
0 resetsystem
interrupt #15 (mid priority)
clear interrupt #15 when 1 is written
6
RegIrqMid[6]
r
c1
0 resetsystem
interrupt #14 (mid priority)
clear interrupt #14 when 1 is written
5
RegIrqMid[5]
r
c1
0 resetsystem
interrupt #13 (mid priority)
clear interrupt #13 when 1 is written
4
RegIrqMid[4]
r
c1
0 resetsystem
interrupt #12 (mid priority)
clear interrupt #12 when 1 is written
3
RegIrqMid[3]
r
c1
0 resetsystem
interrupt #11 (mid priority)
clear interrupt #11 when 1 is written
2
RegIrqMid[2]
r
c1
0 resetsystem
interrupt #10 (mid priority)
clear interrupt #10 when 1 is written
1
RegIrqMid[1]
r
c1
0 resetsystem
interrupt #9 (mid priority)
clear interrupt #9 when 1 is written
0
RegIrqMid[0]
r
c1
0 resetsystem
interrupt #8 (mid priority)
clear interrupt #8 when 1 is written
Table 8-2: RegIrqMid
pos.
RegIrqLow
rw
reset
function
7
RegIrqLow[7]
r
c1
0 resetsystem
interrupt #7 (low priority)
clear interrupt #7 when 1 is written
6
RegIrqLow[6]
r
c1
0 resetsystem
interrupt #6 (low priority)
clear interrupt #6 when 1 is written
5
RegIrqLow[5]
r
c1
0 resetsystem
interrupt #5 (low priority)
clear interrupt #5 when 1 is written
4
RegIrqLow[4]
r
c1
0 resetsystem
interrupt #4 (low priority)
clear interrupt #4 when 1 is written
3
RegIrqLow[3]
r
c1
0 resetsystem
interrupt #3 (low priority)
clear interrupt #3 when 1 is written
2
RegIrqLow[2]
r
c1
0 resetsystem
interrupt #2 (low priority)
clear interrupt #2 when 1 is written
1
RegIrqLow[1]
r
c1
0 resetsystem
interrupt #1 (low priority)
clear interrupt #1 when 1 is written
0
RegIrqLow[0]
r
c1
0 resetsystem
interrupt #0 (low priority)
clear interrupt #0 when 1 is written
Table 8-3: RegIrqLow
pos.
RegIrqEnHig
rw
reset
function
7
RegIrqEnHig[7]
rw
0 resetsystem
1= enable interrupt #23
6
RegIrqEnHig[6]
rw
0 resetsystem
1= enable interrupt #22
5
RegIrqEnHig[5]
rw
0 resetsystem
1= enable interrupt #21
4
RegIrqEnHig[4]
rw
0 resetsystem
1= enable interrupt #20
3
RegIrqEnHig[3]
rw
0 resetsystem
1= enable interrupt #19
2
RegIrqEnHig[2]
rw
0 resetsystem
1= enable interrupt #18
1
RegIrqEnHig[1]
rw
0 resetsystem
1= enable interrupt #17
0
RegIrqEnHig[0]
rw
0 resetsystem
1= enable interrupt #16
Table 8-4: RegIrqEnHig
Not
Recommended
for
New
Designs
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