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參數(shù)資料
| 型號： | XR16C864 |
| 廠商： | Exar Corporation |
| 元件分類： | 通用總線功能 |
| 英文描述： | Quad UART with RX/TX FIFO Counters and 128-byte FIFO(四通用異步接收器/發(fā)送器（帶RX/TX 先進先出計數(shù)器和128字節(jié)先進先出）) |
| 中文描述： | 四路與異步接收/發(fā)送FIFO的計數(shù)器和128字節(jié)的FIFO（四通用異步接收器/發(fā)送器（帶了Rx / Tx先進先出計數(shù)器和128字節(jié)先進先出）） |
| 文件頁數(shù)： | 14/46頁 |
| 文件大小： | 381K |
| 代理商： | XR16C864 |
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XR16C864
14
Rev. 1.10
FIFO Operation
The 128 byte transmit and receive data FIFO’s are
enabled by the FIFO Control Register (FCR) bit-0. With
16C554 devices, the user can set the receive trigger
level but not the transmit trigger level. The 864 provides
independent trigger evels for both receiver and transmit-
ter. To remain compatible with ST16C554, the transmit
interrupt trigger level is set to 1 following a reset. It
should be noted that the user needs to set EFR bit-4 to
1 before setting the transmit trigger levels (FCR bits 4-
5). The receiver FIFO section includes a time-out
function to ensure data is delivered to the external CPU.
An interrupt is generated whenever the Receive Holding
Register (RHR) has not been read following the loading
of a character or the receive trigger level has not been
reached. (see Timeout Interrupt for a description of this
timing).
Hardware Flow Control
When automatic hardware flow control is enabled, the
864 monitors the -CTS pin for a remote buffer overflow
indication and controls the -RTS pin for local buffer
overflows. Automatic hardware flow control is se-
lected by setting bits 6 (RTS) and 7 (CTS) of the EFR
register to a logic 1. If -CTS transitions from a logic 0
to a logic 1 indicating a flow control request, ISR bit-
5 will be set to a logic 1 (if enabled via IER bit 6-7), and
the 864 will suspend TX transmissions as soon as the
stop bit of the character in process is shifted out.
Transmission is resumed after the -CTS input returns to
a logic 0, indicating more data may be sent.
With the Auto RTS function enabled, an interrupt is
generated when the receive FIFO reaches the pro-
grammed trigger level. The -RTS pin will not be forced
to a logic 1 (RTS Off), until the receive FIFO reaches
the next trigger level
.
The -RTS pin will return to a logic
0 after the data buffer (FIFO) is unloaded to the next
trigger level below the programmed trigger. However,
under the above described conditions the 864 will
continue to accept data until the receive FIFO is full. For
example, the table below shows these levels for the
case when 654 trigger levels are selected.
Selected
Trigger
Level
(characters)
INT
Pin
-RTS
Logic “1”
(characters)
-RTS
Logic “0”
(characters)
Send
XOFF
Character
Send
XON
Character
Activation
8
16
56
60
8
16
56
60
16
56
60
60
0
8
16
56
8
16
56
60
0
8
16
56
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| XR16L2450 | 2.25V TO 5.5V DUART |
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| XR16C864CQ | 制造商:Rochester Electronics LLC 功能描述: 制造商:Exar Corporation 功能描述: |
| XR16C864CQ-0A-EVB | 功能描述:UART 接口集成電路 Supports C864 100 ld QFP, ISA Interface RoHS:否 制造商:Texas Instruments 通道數(shù)量:2 數(shù)據(jù)速率:3 Mbps 電源電壓-最大:3.6 V 電源電壓-最小:2.7 V 電源電流:20 mA 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 封裝 / 箱體:LQFP-48 封裝:Reel |
| XR16C864CQ-0B-EB | 功能描述:界面開發(fā)工具 Eval Board for XR16C864CQ Series RoHS:否 制造商:Bourns 產(chǎn)品:Evaluation Boards 類型:RS-485 工具用于評估:ADM3485E 接口類型:RS-485 工作電源電壓:3.3 V |
| XR16C864CQ-F | 功能描述:UART 接口集成電路 UART RoHS:否 制造商:Texas Instruments 通道數(shù)量:2 數(shù)據(jù)速率:3 Mbps 電源電壓-最大:3.6 V 電源電壓-最小:2.7 V 電源電流:20 mA 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 封裝 / 箱體:LQFP-48 封裝:Reel |
| XR16C864CQTR-F | 功能描述:UART 接口集成電路 UART RoHS:否 制造商:Texas Instruments 通道數(shù)量:2 數(shù)據(jù)速率:3 Mbps 電源電壓-最大:3.6 V 電源電壓-最小:2.7 V 電源電流:20 mA 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 封裝 / 箱體:LQFP-48 封裝:Reel |
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