參數(shù)資料
型號: XR16C864
廠商: Exar Corporation
元件分類: 通用總線功能
英文描述: Quad UART with RX/TX FIFO Counters and 128-byte FIFO(四通用異步接收器/發(fā)送器(帶RX/TX 先進先出計數(shù)器和128字節(jié)先進先出))
中文描述: 四路與異步接收/發(fā)送FIFO的計數(shù)器和128字節(jié)的FIFO(四通用異步接收器/發(fā)送器(帶了Rx / Tx先進先出計數(shù)器和128字節(jié)先進先出))
文件頁數(shù): 30/46頁
文件大?。?/td> 381K
代理商: XR16C864
XR16C864
30
Rev. 1.10
MSR BIT-2:
Logic 0 = No -RI Change. (normal default condition)
Logic 1 = The -RI input to the 864 has changed from a
logic 0 to a logic 1. A modem Status Interrupt will be
generated.
MSR BIT-3:
Logic 0 = No -CD Change. (normal default condition)
Logic 1 = Indicates that the -CD input to the has
changed state since the last time it was read. A
modem Status Interrupt will be generated.
MSR BIT-4:
-CTS functions as hardware flow control signal input if
it is enabled via EFR bit-7. The transmit holding
register flow control is enabled/disabled by MSR bit-4.
Flow control (when enabled) allows the starting and
stopping the transmissions based on the external
modem -CTS signal. A logic 1 at the -CTS pin will stop
864 transmissions as soon as current character has
finished transmission.
Normally MSR bit-4 bit is the compliment of the -CTS
input. However in the loop-back mode, this bit is
equivalent to the RTS bit in the MCR register.
MSR BIT-5:
DSR (active high, logical 1). Normally this bit is the
compliment of the -DSR input. In the loop-back mode,
this bit is equivalent to the DTR bit in the MCR register.
MSR BIT-6:
RI (active high, logical 1). Normally this bit is the
compliment of the -RI input. In the loop-back mode
this bit is equivalent to the OP1 bit in the MCR register.
MSR BIT-7:
CD (active high, logical 1). Normally this bit is the
compliment of the -CD input. In the loop-back mode
this bit is equivalent to the OP2 bit in the MCR register.
Scratchpad Register (SPR)
The XR16C864 provides a temporary data register to
store 8 bits of user information.
Enhanced Feature Register (EFR)
Enhanced features are enabled or disabled using this
register.
Bits-0 through 3 provide single or dual character soft-
ware flow control selection (see table 8). When the Xon1
and Xon2 and/or Xoff1 and Xoff2 modes are selected, the
double 8-bit words are concatenated into two sequential
characters.
EFR BIT 0-3: (logic 0 or cleared is the default condi-
tion)
Combinations of software flow control can be selected
by programming these bits. (See Table 6).
EFR BIT-4:
Enhanced function control bit. The content of the IER
bits 4-7, ISR bits 4-5, FCR bits 4-5, and MCR bits 5-7
can be modified and latched. After modifying any bits in
the enhanced registers, EFR bit-4 can be set to a logic
0 to latch the new values. This feature prevents existing
software from altering or overwriting the 864 enhanced
functions.
Logic 0 = Disables the ability to write to IER bits 4-7,
ISR bits 4-5, FCR bits 4-5, and MCR bits 5-7. After a
reset, these bits are set to a logic 0 to be compatible
with ST16C554 mode. (normal default condition).
Logic 1 = Enables the ability to write to the bits
mentioned above.
EFR BIT-5:
Logic 0 = Special Character Detect Disabled. (normal
default condition)
Logic 1 = Special Character Detect Enabled. The 864
compares each incoming receive character with Xoff-2
data. If a match exists, the received data will be
transferred to FIFO and ISR bit-4 will be set to indicate
detection of special character. Bit-0 in the X-registers
corresponds with the LSB bit for the receive character.
When this feature is enabled, the normal software flow
control must be disabled (EFR bits 0-3 must be set to
a logic 0).
EFR BIT-6:
Automatic RTS may be used for hardware flow control
by enabling EFR bit-6. When AUTO RTS is selected, an
interrupt will be generated when the receive FIFO is filled
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