- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄376454 > XR16C864 (Exar Corporation) Quad UART with RX/TX FIFO Counters and 128-byte FIFO(四通用異步接收器/發(fā)送器（帶RX/TX 先進先出計數(shù)器和128字節(jié)先進先出）) PDF資料下載
參數(shù)資料
| 型號： | XR16C864 |
| 廠商： | Exar Corporation |
| 元件分類： | 通用總線功能 |
| 英文描述： | Quad UART with RX/TX FIFO Counters and 128-byte FIFO(四通用異步接收器/發(fā)送器（帶RX/TX 先進先出計數(shù)器和128字節(jié)先進先出）) |
| 中文描述： | 四路與異步接收/發(fā)送FIFO的計數(shù)器和128字節(jié)的FIFO（四通用異步接收器/發(fā)送器（帶了Rx / Tx先進先出計數(shù)器和128字節(jié)先進先出）） |
| 文件頁數(shù)： | 24/46頁 |
| 文件大小： | 381K |
| 代理商： | XR16C864 |
第1頁第2頁第3頁第4頁第5頁第6頁第7頁第8頁第9頁第10頁第11頁第12頁第13頁第14頁第15頁第16頁第17頁第18頁第19頁第20頁第21頁第22頁第23頁當前第24頁第25頁第26頁第27頁第28頁第29頁第30頁第31頁第32頁第33頁第34頁第35頁第36頁第37頁第38頁第39頁第40頁第41頁第42頁第43頁第44頁第45頁第46頁
XR16C864
24
Rev. 1.10
the trigger level (if FIFO is enabled) and is associated
with bit-1 in the LSR register.
Logic 0 = Disable the transmitter empty interrupt.
(normal default condition)
Logic 1 = Enable the transmitter empty interrupt.
IER BIT-2:
This interrupt will be issued whenever a receive data
error condition exists as reflected in LSR bits 1-4.
Logic 0 = Disable the receiver line status interrupt.
(normal default condition)
Logic 1 = Enable the receiver line status interrupt.
IER BIT-3:
Logic 0 = Disable the modem status register interrupt.
(normal default condition)
Logic 1 = Enable the modem status register interrupt.
IER BIT -4:
Logic 0 = Disable sleep mode. (normal default condi-
tion)
Logic 1 = Enable sleep mode. See Sleep Mode section
for details.
IER BIT-5:
Logic 0 = Disable the software flow control, receive
Xoff interrupt. (normal default condition)
Logic 1 = Enable the software flow control, receive
Xoff interrupt. See Software Flow Control section for
details.
IER BIT-6:
Logic 0 = Disable the RTS interrupt. (normal default
condition)
Logic 1 = Enable the RTS interrupt. The 864 issues an
interrupt when the RTS pin transitions from a logic 0
to a logic 1.
IER BIT-7:
Logic 0 = Disable the CTS interrupt. (normal default
condition)
Logic 1 = Enable the CTS interrupt. The 864 issues an
interrupt when CTS pin transitions from a logic 0 to a
logic 1.
FIFO Control Register (FCR)
This register is used to enable the FIFO’s, clear the
FIFO’s, set the transmit/receive FIFO trigger levels, and
select the DMA mode. The DMA, and FIFO modes are
defined as follows:
DMA MODE
Mode 0
transmit or receive operation, and is similar to the
ST16C454 mode. Transmit Ready (-TXRDY) will go to a
logic 0 whenever the TX FIFO is empty. Receive Ready
(-RXRDY) will go to a logic 0 whenever the Receive
Holding Register (RHR) is loaded with a character.
Mode 1
Set and enable the interrupt in a block
mode operation. The transmit interrupt is set when the
transmit FIFO is below the programmed trigger level.
-TXRDY remains a logic 0 as long as one empty FIFO
location is available. The receive interrupt is set when
the receive FIFO fills to the programmed trigger level.
However the FIFO continues to fill regardless of the
programmed level until the FIFO is full. -RXRDY
remains a logic 0 as long as the FIFO fill level is above
the programmed trigger level.
Set and enable the interrupt for each single
FCR BIT-0:
Logic 0 = Disable the transmit and receive FIFO.
(normal default condition)
Logic 1 = Enable the transmit and receive FIFO. This
bit must be a “1” when other FCR bits are written to or
they will not be programmed.
FCR BIT-1:
Logic 0 = No FIFO receive reset. (normal default
condition)
Logic 1 = Clears the contents of the receive FIFO and
resets the FIFO counter logic (the receive shift regis-
ter is not cleared or altered).
FCR BIT-2:
Logic 0 = No FIFO transmit reset. (normal default
condition)
Logic 1 = Clears the contents of the transmit FIFO and
resets the FIFO counter logic (the transmit shift regis-
ter is not cleared or altered).
FCR BIT-3:
Logic 0 = Set DMA mode “0”. (normal default condition)
Logic 1 = Set DMA mode “1.”
Transmit operation n mode “0”:
When the 864 is in the ST16C450 mode (FIFO’s
相關PDF資料 |
PDF描述 |
|---|---|
| XR16C872 | Dual UART with 1284 Parallel Port and Plug-and-Play（PnP） Controller(雙通用異步接收器/發(fā)送器（帶1284雙向并行端口和即插即用控制器）) |
| XR16L2450 | 2.25V TO 5.5V DUART |
| XR16L2450IJ | 97-3108A20-29S-KIT |
| XR16L2450IM | 2.25V TO 5.5V DUART |
| XR16L2550IJ | LOW VOLTAGE DUART WITH 16-BYTE FIFO |
相關代理商/技術參數(shù) |
參數(shù)描述 |
|---|---|
| XR16C864CQ | 制造商:Rochester Electronics LLC 功能描述: 制造商:Exar Corporation 功能描述: |
| XR16C864CQ-0A-EVB | 功能描述:UART 接口集成電路 Supports C864 100 ld QFP, ISA Interface RoHS:否 制造商:Texas Instruments 通道數(shù)量:2 數(shù)據(jù)速率:3 Mbps 電源電壓-最大:3.6 V 電源電壓-最小:2.7 V 電源電流:20 mA 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 封裝 / 箱體:LQFP-48 封裝:Reel |
| XR16C864CQ-0B-EB | 功能描述:界面開發(fā)工具 Eval Board for XR16C864CQ Series RoHS:否 制造商:Bourns 產(chǎn)品:Evaluation Boards 類型:RS-485 工具用于評估:ADM3485E 接口類型:RS-485 工作電源電壓:3.3 V |
| XR16C864CQ-F | 功能描述:UART 接口集成電路 UART RoHS:否 制造商:Texas Instruments 通道數(shù)量:2 數(shù)據(jù)速率:3 Mbps 電源電壓-最大:3.6 V 電源電壓-最小:2.7 V 電源電流:20 mA 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 封裝 / 箱體:LQFP-48 封裝:Reel |
| XR16C864CQTR-F | 功能描述:UART 接口集成電路 UART RoHS:否 制造商:Texas Instruments 通道數(shù)量:2 數(shù)據(jù)速率:3 Mbps 電源電壓-最大:3.6 V 電源電壓-最小:2.7 V 電源電流:20 mA 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 封裝 / 箱體:LQFP-48 封裝:Reel |
發(fā)布緊急采購，3分鐘左右您將得到回復。