參數(shù)資料
型號(hào): XR16C864
廠商: Exar Corporation
元件分類: 通用總線功能
英文描述: Quad UART with RX/TX FIFO Counters and 128-byte FIFO(四通用異步接收器/發(fā)送器(帶RX/TX 先進(jìn)先出計(jì)數(shù)器和128字節(jié)先進(jìn)先出))
中文描述: 四路與異步接收/發(fā)送FIFO的計(jì)數(shù)器和128字節(jié)的FIFO(四通用異步接收器/發(fā)送器(帶了Rx / Tx先進(jìn)先出計(jì)數(shù)器和128字節(jié)先進(jìn)先出))
文件頁(yè)數(shù): 28/46頁(yè)
文件大小: 381K
代理商: XR16C864
XR16C864
28
Rev. 1.10
LCR BITS-3:5:
Parity can be programmed using these bits as shown in
the table below:
LCR
Bit-5
LCR
Bit-4
LCR
Bit-3
Parity selection
X
0
0
1
1
X
0
1
0
1
0
1
1
1
1
No parity
Odd parity
Even parity
Force parity “1”
Forced parity “0”
LCR BIT-6:
When enabled, the Break control bit causes a break
condition to be transmitted (the TX output is forced to
a logic 0 state). This condition exists until disabled by
setting LCR bit-6 to a logic 0.
Logic 0 = No TX break condition. (normal default
condition)
Logic 1 = Forces the transmitter output (TX) to a logic
0 for alerting the remote receiver to a line break condi-
tion.
LCR BIT-7:
The internal baud rate counter latch enable.
Logic 0 = Divisor latch disabled. (normal default condi-
tion)
Logic 1 = Divisor latch enabled.
Modem Control Register (MCR)
This register controls the interface with the modem or
a peripheral device.
MCR BIT-0:
Logic 0 = Force -DTR output to a logic 1. (normal
default condition)
Logic 1 = Force -DTR output to a logic 0.
MCR BIT-1:
Logic 0 = Force -RTS output to a logic 1. (normal
default condition)
Logic 1 = Force -RTS output to a logic 0.
Automatic RTS may be used for hardware flow control
by enabling EFR bit-6 (See EFR bit-6).
MCR BIT-2:
This bit is used in the Loop-back mode only. In the
loop-back mode this bit is use to write the state of the
modem -RI interface signal via -OP1.
MCR BIT-3:
This bit is used in conjunction with the INTSEL pin and
can control the INT A-D outputs only when INTSEL is
tied to GND.
Logic 0 = Tri-states the INT (A-D) outputs during the 16
mode. (normal default condition). In the Loop-back
mode, sets -OP2 (-CD) internally to a logic 1.
Logic 1 = Forces the INT (A-D) outputs to the active
mode during the 16 mode. In the Loop-back mode,
sets -OP2 (-CD) internally to a logic 0.
MCR BIT-4:
Logic 0 = Disable loop-back mode. (normal default
condition)
Logic 1 = Enable local loop-back mode (diagnostics).
MCR BIT-5:
Logic 0 = Disable Xon any function (for 16C550 compat-
ibility). (normal default condition)
Logic 1 = Enable Xon any function. In this mode any RX
character received will enable the transmitter.
MCR BIT-6:
Logic 0 = Enable the standard modem receive and
transmit input/output interface. (normal default condi-
tion)
Logic 1 = Enable infrared IrDA receive and transmit
inputs/outputs. While in this mode, the TX/RX output/
Inputs are routed to the infrared encoder/decoder. The
data input and output levels will conform to the IrDA 1.0
infrared interface requirement. As such, while in this
mode the infrared TX output will be a logic 0 during idle
data conditions.
MCR BIT-7:
Logic 0 = Divide by one. The input clock (crystal or
external) is divided by sixteen and then presented to
the Programmable Baud Rate Generator (BGR) with-
out further modification, i.e., divide by one. (normal,
default condition)
Logic 1 = Divide by four. The divide by one clock
described above is further divided by four (also see
Programmable Baud Rate Generator section).
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