參數(shù)資料
型號: XR16C864
廠商: Exar Corporation
元件分類: 通用總線功能
英文描述: Quad UART with RX/TX FIFO Counters and 128-byte FIFO(四通用異步接收器/發(fā)送器(帶RX/TX 先進先出計數(shù)器和128字節(jié)先進先出))
中文描述: 四路與異步接收/發(fā)送FIFO的計數(shù)器和128字節(jié)的FIFO(四通用異步接收器/發(fā)送器(帶了Rx / Tx先進先出計數(shù)器和128字節(jié)先進先出))
文件頁數(shù): 26/46頁
文件大小: 381K
代理商: XR16C864
XR16C864
26
Rev. 1.10
FCR BIT 6-7: (logic 0 or cleared s he default condition,
RX trigger evel =8)
These bits are used to set the trigger level for the
receiver FIFO interrupt. The FCTR Bits 4-5 selects one
of the following table.
TRIGGER TABLE-A (Receive)
“Default setting after reset ST16C550 mode”
BIT-7
BIT-6
FIFO trigger level
0
0
1
1
0
1
0
1
1
4
8
14
TRIGGER TABLE-B (Receive)
BIT-7
BIT-6
FIFO trigger level
0
0
1
1
0
1
0
1
8
16
24
28
TRIGGER TABLE-C (Receive)
BIT-7
BIT-6
FIFO trigger level
0
0
1
1
0
1
0
1
8
16
56
60
TRIGGER TABLE-D (Receive)
For this setting, set FCTR bit-7 to "0" and program the
TRG register (in the Enhanced Register Set) with the
required trigger level. In this case, FCR bits 6 and 7 do
not control the RX FIFO trigger level.
TRG
BITS 7 to 0
FIFO trigger level
0xXX
User programmable
Trigger evels
Interrupt Status Register (ISR)
The 864 provides six levels of prioritized interrupts to
minimize external software interaction. The Interrupt
Status Register (ISR) provides the user with six interrupt
status bits. Performing a read cycle on the ISR will
provide the user with the highest pending interrupt level
to be serviced. No other interrupts are acknowledged
until the pending interrupt is serviced. Whenever the
interrupt status register is read, the interrupt status is
cleared. However it should be noted that only the current
pending interrupt is cleared by the read. A lower level
interrupt may be seen after rereading the interrupt
status bits. The Interrupt Source Table 5 (below) shows
the data values (bit 0-5) for the six prioritized interrupt
levels and the interrupt sources associated with each of
these interrupt levels:
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