參數(shù)資料
型號(hào): XR16C864
廠商: Exar Corporation
元件分類: 通用總線功能
英文描述: Quad UART with RX/TX FIFO Counters and 128-byte FIFO(四通用異步接收器/發(fā)送器(帶RX/TX 先進(jìn)先出計(jì)數(shù)器和128字節(jié)先進(jìn)先出))
中文描述: 四路與異步接收/發(fā)送FIFO的計(jì)數(shù)器和128字節(jié)的FIFO(四通用異步接收器/發(fā)送器(帶了Rx / Tx先進(jìn)先出計(jì)數(shù)器和128字節(jié)先進(jìn)先出))
文件頁(yè)數(shù): 27/46頁(yè)
文件大小: 381K
代理商: XR16C864
XR16C864
27
Rev. 1.10
Table 5, INTERRUPT SOURCE TABLE
Priority
Level
[ ISR BITS ]
Bit-5 Bit-4 Bit-3 Bit-2 Bit-1 Bit-0
Source of the interrupt
X
1
2
2
3
4
5
6
0
0
0
0
0
0
0
1
0
0
0
0
0
0
1
0
0
0
0
1
0
0
0
0
0
1
1
1
0
0
0
0
0
1
0
0
1
0
0
0
1
0
0
0
0
0
0
0
None
LSR (Receiver Line Status Register)
RXRDY (Received Data Ready)
RXRDY (Receive Data time out)
TXRDY ( Transmitter Holding Register Empty)
MSR (Modem Status Register)
RXRDY (Received Xoff signal)/ Special character
CTS, RTS change of state
ISR BIT-0:
Logic 0 = An interrupt is pending and the ISR contents
may be used as a pointer to the appropriate interrupt
service routine.
Logic 1 = No interrupt pending. (normal default condi-
tion)
ISR BIT 1-3: (logic 0 or cleared s the default condition)
These bits indicate the source for a pending interrupt
at interrupt priority levels 1, 2, and 3 (See Interrupt
Source Table).
ISR BIT 4-5: (logic 0 or cleared s the default condition)
These bits are enabled when EFR bit-4 is set to a logic
1. ISR bit-4 indicates that matching Xoff character(s)
have been detected. ISR bit-5 indicates that CTS,
RTS have been generated. Note that once set to a logic
1, the ISR bit-4 will stay a logic 1 until Xon character(s)
are received.
ISR BIT 6-7: (logic 0 or cleared s the default condition)
These bits are set to a logic 0 when the FIFO is not
being used. They are set to a logic 1 when the FIFO’s
are enabled.
Line Control Register (LCR)
The Line Control Register is used to specify the asyn-
chronous data communication format. The word length,
the number of stop bits, and the parity are selected by
writing the appropriate bits in this register.
LCR BIT 0-1: (logic 0 or cleared s he default condition)
These two bits specify the word length to be transmitted
or received.
BIT-1
BIT-0
Word length
0
0
1
1
0
1
0
1
5
6
7
8
LCR BIT-2: (logic 0 or cleared is the default condition)
The length of stop bit is specified by this bit in
conjunction with the programmed word length.
BIT-2
Word length
Stop bit
length
(Bit time(s))
0
1
1
5,6,7,8
5
6,7,8
1
1-1/2
2
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