SPNS174A – APRIL 2012 – REVISED SEPTEMBER 2013
RM48Lx50 16- and 32-Bit RISC Flash Microcontroller
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RM48Lx50 16- and 32-Bit RISC Flash Microcontroller
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Features
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– Data Modification Module (DMM)
High-Performance Microcontroller for Safety-
Critical Applications
– RAM Trace Port (RTP)
– Dual CPUs Running in Lockstep
– Parameter Overlay Module (POM)
– ECC on Flash and RAM interfaces
Multiple Communication Interfaces
– Built-In Self-Test for CPU and On-chip RAMs
– 10/100 Mbps Ethernet MAC (EMAC)
– Error Signaling Module with Error Pin
IEEE 802.3 Compliant (3.3-V I/O only)
– Voltage and Clock Monitoring
Supports MII, RMII and MDIO
ARM Cortex – R4F 32-Bit RISC CPU
– USB
– Efficient 1.66 DMIPS/MHz with 8-Stage
2-Port USB Host Controller
Pipeline
One Full-Speed USB Device Port
– FPU with Single- and Double-Precision
– Three CAN Controllers (DCANs)
– 12-Region Memory Protection Unit
64 Mailboxes, Each with Parity Protection
– Open Architecture with Third-Party Support
Compliant to CAN Protocol Version 2.0B
Operating Conditions
– Local Interconnect Network (LIN) Interface
– Up to 200-MHz System Clock
Controller
– Core Supply Voltage (VCC): 1.2 V Nominal
Compliant to LIN Protocol Version 2.1
– I/O Supply Voltage (VCCIO): 3.3 V Nominal
Can be Configured as a Second SCI
– ADC Supply Voltage (VCCAD): 3.0 to 5.25 V
– Standard Serial Communication Interface
(SCI)
Integrated Memory
– Inter-Integrated Circuit (I2C)
– Up to 3MB of Program Flash with ECC
– Three Multibuffered Serial Peripheral
– Up to 256KB of RAM with ECC
Interfaces (MibSPIs)
– 64KB of Flash with ECC for Emulated
128 Words with Parity Protection Each
EEPROM
– Two Standard Serial Peripheral Interfaces
16-Bit External Memory Interface
(SPIs)
Common Platform Architecture
Two High-End Timer Modules (N2HETs)
– Consistent Memory Map Across Family
– N2HET1: 32 Programmable Channels
– Real-Time Interrupt Timer (RTI) OS Timer
– N2HET2: 18 Programmable Channels
– 96-Channel Vectored Interrupt Module (VIM)
– 160-Word Instruction RAM with Parity
– 2-Channel Cyclic Redundancy Checker
Protection Each
(CRC)
– Each N2HET Includes Hardware Angle
Direct Memory Access (DMA) Controller
Generator
– 16 Channels and 32 Control Packets
– Dedicated Transfer Unit with MPU for Each
– Parity Protection for Control Packet RAM
N2HET (HTU)
– DMA Accesses Protected by Dedicated MPU
Two 10- or 12-bit Multibuffered ADC Modules
Frequency-Modulated Phase-Locked-Loop
– ADC1: 24 Channels
(FMPLL) with Built-In Slip Detector
– ADC2: 16 Channels Shared with ADC1
Separate Nonmodulating PLL
– 64 Result Buffers with Parity Protection Each
IEEE 1149.1 JTAG, Boundary Scan and ARM
Sixteen General-Purpose Input/Output Pins
CoreSight Components
(GPIO) Capable of Generating Interrupts
JTAG Security Module
Packages
Trace and Calibration Capabilities
– 144-Pin Quad Flatpack (PGE) [Green]
– Embedded Trace Macrocell (ETM-R4)
– 337-Ball Grid Array (ZWT) [Green]
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2
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PRODUCTION DATA information is current as of publication date. Products conform to
Copyright 2012–2013, Texas Instruments Incorporated
specifications per the terms of the Texas Instruments standard warranty. Production
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