參數(shù)資料
型號(hào)： XRM48L950ZWTT
廠商： Texas Instruments
文件頁數(shù)： 56/176頁
文件大小： 0K
描述： MCU 16/32Bit FLASH 3MB 337NFBGA
標(biāo)準(zhǔn)包裝： 1
系列： Hercules™ ARM® RM4x
應(yīng)用： 工業(yè)安全，醫(yī)療
核心處理器： ARM? Cortex? - R4F
程序存儲(chǔ)器類型： 閃存（3MB）
控制器系列： RM4
RAM 容量： 256K x 8
接口： CAN，以太網(wǎng)，I²C，LIN，MibSPI，SCI，SPI，USB
輸入/輸出數(shù)： 120
電源電壓： 1.14 V ~ 3.6 V
工作溫度： -40°C ~ 105°C
安裝類型： 表面貼裝
封裝/外殼： 337-LFBGA
包裝： 托盤
供應(yīng)商設(shè)備封裝： 337-NFBGA（16x16）
其它名稱： 296-29390
SPNS174A – APRIL 2012 – REVISED SEPTEMBER 2013
5.9.4
MibSPI/SPI Master Mode I/O Timing Specifications
Table 5-22. SPI Master Mode External Timing Parameters (CLOCK PHASE = 0, SPICLK = output, SPISIMO
= output, and SPISOMI = input)(1)(2)(3)
NO.
Parameter
MIN
MAX
Unit
1
tc(SPC)M
Cycle time, SPICLK(4)
40
256tc(VCLK)
ns
2(5)
tw(SPCH)M
Pulse duration, SPICLK high (clock
0.5tc(SPC)M – tr(SPC)M – 3
0.5tc(SPC)M + 3
ns
polarity = 0)
tw(SPCL)M
Pulse duration, SPICLK low (clock
0.5tc(SPC)M – tf(SPC)M – 3
0.5tc(SPC)M + 3
polarity = 1)
3(5)
tw(SPCL)M
Pulse duration, SPICLK low (clock
0.5tc(SPC)M – tf(SPC)M – 3
0.5tc(SPC)M + 3
ns
polarity = 0)
tw(SPCH)M
Pulse duration, SPICLK high (clock
0.5tc(SPC)M – tr(SPC)M – 3
0.5tc(SPC)M + 3
polarity = 1)
4(5)
td(SPCH-SIMO)M
Delay time, SPISIMO valid before
0.5tc(SPC)M – 6
ns
SPICLK low (clock polarity = 0)
td(SPCL-SIMO)M
Delay time, SPISIMO valid before
0.5tc(SPC)M – 6
SPICLK high (clock polarity = 1)
5(5)
tv(SPCL-SIMO)M
Valid time, SPISIMO data valid after
0.5tc(SPC)M – tf(SPC) – 4
ns
SPICLK low (clock polarity = 0)
tv(SPCH-SIMO)M
Valid time, SPISIMO data valid after
0.5tc(SPC)M – tr(SPC) – 4
SPICLK high (clock polarity = 1)
6(5)
tsu(SOMI-SPCL)M
Setup time, SPISOMI before SPICLK
tf(SPC) + 2.2
ns
low (clock polarity = 0)
tsu(SOMI-SPCH)M Setup time, SPISOMI before SPICLK
tr(SPC) + 2.2
high (clock polarity = 1)
7(5)
th(SPCL-SOMI)M
Hold time, SPISOMI data valid after
10
ns
SPICLK low (clock polarity = 0)
th(SPCH-SOMI)M
Hold time, SPISOMI data valid after
10
SPICLK high (clock polarity = 1)
8(6)
tC2TDELAY
Setup time CS active
CSHOLD = 0
C2TDELAY*tc(VCLK) + 2*tc(VCLK)
(C2TDELAY+2) * tc(VCLK) -
ns
until SPICLK high
- tf(SPICS) + tr(SPC) – 7
tf(SPICS) + tr(SPC) + 5.5
(clock polarity = 0)
CSHOLD = 1
C2TDELAY*tc(VCLK) + 3*tc(VCLK)
(C2TDELAY+3) * tc(VCLK) -
- tf(SPICS) + tr(SPC) – 7
tf(SPICS) + tr(SPC) + 5.5
Setup time CS active
CSHOLD = 0
C2TDELAY*tc(VCLK) + 2*tc(VCLK)
(C2TDELAY+2) * tc(VCLK) -
ns
until SPICLK low
- tf(SPICS) + tf(SPC) – 7
tf(SPICS) + tf(SPC) + 5.5
(clock polarity = 1)
CSHOLD = 1
C2TDELAY*tc(VCLK) + 3*tc(VCLK)
(C2TDELAY+3) * tc(VCLK) -
- tf(SPICS) + tf(SPC) – 7
tf(SPICS) + tf(SPC) + 5.5
9(6)
tT2CDELAY
Hold time SPICLK low until CS inactive
0.5*tc(SPC)M +
ns
(clock polarity = 0)
T2CDELAY*tc(VCLK) + tc(VCLK) -
tf(SPC) + tr(SPICS) - 7
tf(SPC) + tr(SPICS) + 11
Hold time SPICLK high until CS
0.5*tc(SPC)M +
ns
inactive (clock polarity = 1)
T2CDELAY*tc(VCLK) + tc(VCLK) -
tr(SPC) + tr(SPICS) - 7
tr(SPC) + tr(SPICS) + 11
10
tSPIENA
SPIENAn Sample point
(C2TDELAY+1) * tc(VCLK) -
(C2TDELAY+1)*tc(VCLK)
ns
tf(SPICS) – 29
11
tSPIENAW
SPIENAn Sample point from write to
(C2TDELAY+2)*tc(VCLK)
ns
buffer
(1)
The MASTER bit (SPIGCR1.0) is set and the CLOCK PHASE bit (SPIFMTx.16) is cleared.
(2)
tc(VCLK) = interface clock cycle time = 1 / f(VCLK)
(3)
For rise and fall timings, see Table 3-5.
(4)
When the SPI is in Master mode, the following must be true:
For PS values from 1 to 255: tc(SPC)M ≥ (PS +1)tc(VCLK) ≥ 40ns, where PS is the prescale value set in the SPIFMTx.[15:8] register bits.
For PS values of 0: tc(SPC)M = 2tc(VCLK) ≥ 40ns.
The external load on the SPICLK pin must be less than 60pF.
(5)
The active edge of the SPICLK signal referenced is controlled by the CLOCK POLARITY bit (SPIFMTx.17).
(6)
C2TDELAY and T2CDELAY is programmed in the SPIDELAY register
Copyright 2012–2013, Texas Instruments Incorporated
Peripheral Information and Electrical Specifications
149
Product Folder Links: RM48L950 RM48L750 RM48L550
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