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SPNS174A – APRIL 2012 – REVISED SEPTEMBER 2013
1
RM48Lx50 16- and 32-Bit RISC Flash
4.9
Device Memory Map
................................
74Microcontroller
.......................................... 1 4.10
Flash Memory
......................................
811.1
Features
.............................................
14.11
Tightly-Coupled RAM Interface Module
1.2
Applications
..........................................
24.12
Parity Protection for peripheral RAMs
1.3
Description
...........................................
34.13
On-Chip SRAM Initialization and Testing
1.4
Functional Block Diagram
...........................
54.14
External Memory Interface (EMIF)
Revision History
.............................................. 7 4.15
Vectored Interrupt Manager
........................
962
Device Package and Terminal Functions
4.16
DMA Controller
.....................................
992.1
PGE QFP Package Pinout (144-Pin)
4.17
Real Time Interrupt Module
.......................
1022.2
ZWT BGA Package Ball-Map (337 Ball Grid Array)
4.18
Error Signaling Module
............................
1042.3
Terminal Functions
.................................
114.19
Reset / Abort / Error Sources
.....................
1083
Device Operating Conditions
....................... 46 4.20
Digital Windowed Watchdog
......................
1103.1
Absolute Maximum Ratings Over Operating Free-
4.21
Debug Subsystem
.................................
111Air Temperature Range,
............................
465
Peripheral Information and Electrical
3.2
Device Recommended Operating Conditions
Specifications
......................................... 122 3.3
Switching Characteristics over Recommended
5.1
Peripheral Legend
................................
122Operating Conditions for Clock Domains
5.2
Multi-Buffered 12bit Analog-to-Digital Converter
3.4
Wait States Required
...............................
475.3
General-Purpose Input/Output
3.5
Power Consumption Over Recommended
5.4
Enhanced High-End Timer (N2HET)
Operating Conditions
...............................
485.5
Controller Area Network (DCAN)
3.6
Input/Output Electrical Characteristics Over
Recommended Operating Conditions
5.6
Local Interconnect Network Interface (LIN)
3.7
Output Buffer Drive Strengths
......................
495.7
Serial Communication Interface (SCI)
3.8
Input Timings
.......................................
505.8
Inter-Integrated Circuit (I2C)
......................
1423.9
Output Timings
.....................................
515.9
Multi-Buffered / Standard Serial Peripheral Interface
.....................................................
1453.10
Low-EMI Output Buffers
............................
535.10
Ethernet Media Access Controller
4
System Information and Electrical Specifications
............................................................. 55 5.11
Universal Serial Bus Controller
4.1
Device Power Domains
............................
556
Device and Documentation Support
4.2
Voltage Monitor Characteristics
6.1
Device Nomenclature
.............................
1634.3
Power Sequencing and Power On Reset
6.2
Device Identification
...............................
1644.4
Warm Reset (nRST)
................................
596.3
Module Certifications
..............................
1664.5
ARM Cortex-R4F CPU Information
7
Mechanical Data
...................................... 171 4.6
Clocks
..............................................
637.1
Thermal Data
......................................
1714.7
Clock Monitoring
....................................
717.2
Packaging Information
............................
1714.8
Glitch Filters
........................................
736
Contents
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