參數(shù)資料
型號: XRM48L950ZWTT
廠商: Texas Instruments
文件頁數(shù): 162/176頁
文件大?。?/td> 0K
描述: MCU 16/32Bit FLASH 3MB 337NFBGA
標(biāo)準(zhǔn)包裝: 1
系列: Hercules™ ARM® RM4x
應(yīng)用: 工業(yè)安全,醫(yī)療
核心處理器: ARM? Cortex? - R4F
程序存儲器類型: 閃存(3MB)
控制器系列: RM4
RAM 容量: 256K x 8
接口: CAN,以太網(wǎng),I²C,LIN,MibSPI,SCI,SPI,USB
輸入/輸出數(shù): 120
電源電壓: 1.14 V ~ 3.6 V
工作溫度: -40°C ~ 105°C
安裝類型: 表面貼裝
封裝/外殼: 337-LFBGA
包裝: 托盤
供應(yīng)商設(shè)備封裝: 337-NFBGA(16x16)
其它名稱: 296-29390
SPNS174A – APRIL 2012 – REVISED SEPTEMBER 2013
4.13 On-Chip SRAM Initialization and Testing
4.13.1 On-Chip SRAM Self-Test Using PBIST
4.13.1.1 Features
Extensive instruction set to support various memory test algorithms
ROM-based algorithms allow application to run TI production-level memory tests
Independent testing of all on-chip SRAM
4.13.1.2 PBIST RAM Groups
Table 4-25. PBIST RAM Grouping
Test Pattern (Algorithm)
March 13N(1)
triple read
two port
single port
Memory
RAM Group
Test Clock
MEM Type
slow read
fast read
(cycles)
ALGO MASK
0x1
0x2
0x4
0x8
PBIST_ROM
1
ROM CLK
ROM
24578
8194
STC_ROM
2
ROM CLK
ROM
19586
6530
DCAN1
3
VCLK
Dual Port
25200
DCAN2
4
VCLK
Dual Port
25200
DCAN3
5
VCLK
Dual Port
25200
ESRAM1
6
HCLK
Single Port
266280
MIBSPI1
7
VCLK
Dual Port
33440
MIBSPI3
8
VCLK
Dual Port
33440
MIBSPI5
9
VCLK
Dual Port
33440
VIM
10
VCLK
Dual Port
12560
MIBADC1
11
VCLK
Dual Port
4200
DMA
12
HCLK
Dual Port
18960
N2HET1
13
VCLK
Dual Port
31680
HTU1
14
VCLK
Dual Port
6480
RTP
15
HCLK
Dual Port
37800
MIBADC2
18
VCLK
Dual Port
4200
N2HET2
19
VCLK
Dual Port
31680
HTU2
20
VCLK
Dual Port
6480
ESRAM5
21
HCLK
Single Port
266280
ESRAM6
22
HCLK
Single Port
266280
23
8700
Dual Port
ETHERNET
24
VCLK3
6360
25
Single Port
133160
26
Dual Port
4240
USB
VCLK3
27
Single Port
66600
ESRAM8
28
HCLK
Single Port
266280
(1)
There are several memory testing algorithms stored in the PBIST ROM. However, TI recommends the March13N algorithm for
application testing.
The PBIST ROM clock frequency is limited to 100MHz, if 100MHz < HCLK <= HCLKmax, or HCLK, if
HCLK <= 100MHz.
The PBIST ROM clock is divided down from HCLK. The divider is selected by programming the ROM_DIV
field of the Memory Self-Test Global Control Register (MSTGCR) at address 0xFFFFFF58.
86
System Information and Electrical Specifications
Copyright 2012–2013, Texas Instruments Incorporated
Product Folder Links: RM48L950 RM48L750 RM48L550
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