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參數(shù)資料
型號(hào): XRM48L950ZWTT
廠商: Texas Instruments
文件頁數(shù): 21/176頁
文件大小: 0K
描述: MCU 16/32Bit FLASH 3MB 337NFBGA
標(biāo)準(zhǔn)包裝: 1
系列: Hercules™ ARM® RM4x
應(yīng)用: 工業(yè)安全,醫(yī)療
核心處理器: ARM? Cortex? - R4F
程序存儲(chǔ)器類型: 閃存(3MB)
控制器系列: RM4
RAM 容量: 256K x 8
接口: CAN,以太網(wǎng),I²C,LIN,MibSPI,SCI,SPI,USB
輸入/輸出數(shù): 120
電源電壓: 1.14 V ~ 3.6 V
工作溫度: -40°C ~ 105°C
安裝類型: 表面貼裝
封裝/外殼: 337-LFBGA
包裝: 托盤
供應(yīng)商設(shè)備封裝: 337-NFBGA(16x16)
其它名稱: 296-29390
tcyc(RTP)
tr
tf
th(RTP)
tl(RTP)
SPNS174A – APRIL 2012 – REVISED SEPTEMBER 2013
4.21.8 RAM Trace Port (RTP)
The RTP provides the ability to datalog the RAM contents of the RM4x devices or accesses to peripherals
without program intrusion. It can trace all data write or read accesses to internal RAM. In addition, it
provides the capability to directly transfer data to a FIFO to support a CPU-controlled transmission of the
data. The trace data is transmitted over a dedicated external interface.
4.21.8.1 Features
The RTP offers the following features:
Two modes of operation - Trace Mode and Direct Data Mode
Trace Mode
Non-intrusive data trace on write or read operation
Visibility of RAM content at any time on external capture hardware
Trace of peripheral accesses
2 configurable trace regions for each RAM module to limit amount of data to be traced
FIFO to store data and address of data of multiple read/write operations
Trace of CPU and/or DMA accesses with indication of the master in the transmitted data packet
Direct Data Mode
Directly write data with the CPU or trace read operations to a FIFO, without transmitting header
and address information
Dedicated synchronous interface to transmit data to external devices
Free-running clock generation or clock stop mode between transmissions
Up to 100 Mbit per sec/pin transfer rate for transmitting data
Pins not used in functional mode can be used as GIOs
4.21.8.2 Timing Specifications
Figure 4-24. RTPCLK Timing
Table 4-44. RTPCLK Timing
Parameter
MIN
Description
tcyc(RTP)
11ns (90MHz)
Clock period, prescaled from HCLK; must not be faster
than HCLK / 2
th(RTP)
((tcyc(RTP))/2) - ((tr+tf)/2)
High pulse width
tl(RTP)
((tcyc(RTP))/2) - ((tr+tf)/2)
Low pulse width
Copyright 2012–2013, Texas Instruments Incorporated
System Information and Electrical Specifications
117
Product Folder Links: RM48L950 RM48L750 RM48L550
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