參數資料
型號: XRM48L950ZWTT
廠商: Texas Instruments
文件頁數: 154/176頁
文件大小: 0K
描述: MCU 16/32Bit FLASH 3MB 337NFBGA
標準包裝: 1
系列: Hercules™ ARM® RM4x
應用: 工業(yè)安全,醫(yī)療
核心處理器: ARM? Cortex? - R4F
程序存儲器類型: 閃存(3MB)
控制器系列: RM4
RAM 容量: 256K x 8
接口: CAN,以太網,I²C,LIN,MibSPI,SCI,SPI,USB
輸入/輸出數: 120
電源電壓: 1.14 V ~ 3.6 V
工作溫度: -40°C ~ 105°C
安裝類型: 表面貼裝
封裝/外殼: 337-LFBGA
包裝: 托盤
供應商設備封裝: 337-NFBGA(16x16)
其它名稱: 296-29390
SPNS174A – APRIL 2012 – REVISED SEPTEMBER 2013
4.9.3
Master/Slave Access Privileges
The table below lists the access permissions for each bus master on the device. A bus master is a module
that can initiate a read or a write transaction on the device.
Each slave module on the main interconnect is listed in the table. A "Yes" indicates that the module listed
in the "MASTERS" column can access that slave module.
Table 4-21. Master / Slave Access Matrix
MASTERS
ACCESS MODE
SLAVES ON MAIN SCR
Flash Module
Non-CPU
CRC
EMIF, Ethernet,
Peripheral
Bus2 Interface:
Accesses to
USB Slave
Control
OTP, ECC,
Program Flash
Interfaces
Registers, All
EEPROM Bank
and CPU Data
Peripheral
RAM
Memories, And
All System
Module Control
Registers And
Memories
CPU READ
User/Privilege
Yes
CPU WRITE
User/Privilege
No
Yes
DMA
User
Yes
POM
User
Yes
DMM
User
Yes
DAP
Privilege
Yes
HTU1
Privilege
No
Yes
HTU2
Privilege
No
Yes
EMAC DMA
User
No
Yes
No
Yes
No
OHCI
User
No
Yes
No
Yes
No
4.9.3.1
Special Notes on Accesses to Certain Slaves
Write accesses to the Power Domain Management Module (PMM) control registers are limited to the CPU
(master id = 1). The other masters can only read from these registers.
A debugger can also write to the PMM registers. The master-id check is disabled in debug mode.
The device contains dedicated logic to generate a bus error response on any access to a module that is in
a power domain that has been turned OFF.
Copyright 2012–2013, Texas Instruments Incorporated
System Information and Electrical Specifications
79
Product Folder Links: RM48L950 RM48L750 RM48L550
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