SPNS174A – APRIL 2012 – REVISED SEPTEMBER 2013
1.3
Description
The RM48Lx50 device is a high-performance microcontroller family for safety systems. The safety
architecture includes the following:
Dual CPUs in lockstep
CPU and memory Built-In Self-Test (BIST) logic
ECC on both the flash and the data SRAM
Parity on peripheral memories
Loopback capability on peripheral I/Os
The RM48Lx50 device integrates the ARM Cortex-R4F Floating-Point CPU which offers an efficient 1.66
DMIPS/MHz, and has configurations which can run up to 200 MHz, providing up to 332 DMIPS. The
device supports the little-endian [LE] format.
The RM48Lx50 device has up to 3MB of integrated flash and up to 256KB of data RAM with single-bit
error correction and double-bit error detection. The flash memory on this device is a nonvolatile,
electrically erasable and programmable memory implemented with a 64-bit-wide data bus interface. The
flash operates on a 3.3-V supply input (same level as I/O supply) for all read, program and erase
operations. When in pipeline mode, the flash operates with a system clock frequency of up to 200 MHz.
The SRAM supports single-cycle read and write accesses in byte, halfword, word and double-word
modes.
The RM48Lx50 device features peripherals for real-time control-based applications, including two Next
Generation High-End Timer (N2HET) timing coprocessors and two 12-bit analog-to-digital converters
(ADCs) supporting up to 24 inputs.
The N2HET is an advanced intelligent timer that provides sophisticated timing functions for real-time
applications. The timer is software-controlled, using a reduced instruction set, with a specialized timer
micromachine and an attached I/O port. The N2HET can be used for pulse-width-modulated outputs,
capture or compare inputs, or GPIO. The N2HET is especially well suited for applications requiring
multiple sensor information and drive actuators with complex and accurate time pulses. A High-End Timer
Transfer Unit (HTU) can perform DMA-type transactions to transfer N2HET data to or from main memory.
A Memory Protection Unit (MPU) is built into the HTU.
The device has two 12-bit-resolution MibADCs with 24 channels and 64 words of parity-protected buffer
RAM each. The MibADC channels can be converted individually or can be grouped by software for
sequential conversion sequences. Sixteen channels are shared between the two MibADCs. There are
three separate groupings. Each sequence can be converted once when triggered or configured for
continuous conversion mode.
The device has multiple communication interfaces: three MibSPIs, two SPIs, one LIN, one SCI, three
DCANs, one I2C, one Ethernet, and one USB module. The SPIs provide a convenient method of serial
high-speed communication between similar shift-register type devices. The LIN supports the Local
Interconnect standard 2.0 and can be used as a UART in full-duplex mode using the standard Non-
Return-to-Zero (NRZ) format.
The DCAN supports the CAN 2.0 (A and B) protocol standard and uses a serial, multimaster
communication protocol that efficiently supports distributed real-time control with robust communication
rates of up to 1 Mbps. The DCAN is ideal for systems operating in noisy and harsh environments (for
example, automotive vehicle networking and industrial fieldbus) that require reliable serial communication
or multiplexed wiring.
The Ethernet module supports MII, RMII and MDIO interfaces.
The USB module includes a 2-port USB host controller. It is revision 2.0-compatible, based on the OHCI
specification for USB, release 1.0. The USB module also includes a USB device controller compatible with
the USB specification revision 2.0 and USB specification revision 1.1.
Copyright 2012–2013, Texas Instruments Incorporated
RM48Lx50 16- and 32-Bit RISC Flash Microcontroller
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