參數(shù)資料
型號： XRT75R06DIB
廠商： EXAR CORP
元件分類： 數(shù)字傳輸電路
英文描述： SIX CHANNEL E3/DS3/STS-1 LINE INTERFACE UNIT WITH SONET DESYNCHRONIZER
中文描述： DATACOM, PCM TRANSCEIVER, PBGA217
封裝： 23 X 23 MM, BGA-217
文件頁數(shù)： 4/105頁
文件大小： 591K
代理商： XRT75R06DIB
XRT75R06D
SIX CHANNEL E3/DS3/STS-1 LINE INTERFACE UNIT WITH SONET DESYNCHRONIZER
á
REV. 1.0.0
I
TABLE OF CONTENTS
GENERAL DESCRIPTION ................................................................................................. 1
A
PPLICATIONS
.............................................................................................................................................. 1
Figure 1. Block Diagram of the XRT 75R06D ................................................................................................... 1
ORDERING INFORMATION ................................................................................................................... 1
F
EATURES
.................................................................................................................................................... 2
T
RANSMIT
I
NTERFACE
C
HARACTERISTICS
...................................................................................................... 2
R
ECEIVE
I
NTERFACE
C
HARACTERISTICS
........................................................................................................ 2
Figure 2. XRT75R06D in BGA package (Bottom View) .................................................................................... 3
TABLE OF CONTENTS .................................................................................................................................... I
PIN DESCRIPTIONS (BY FUNCTION) .............................................................................. 4
T
RANSMIT
I
NTERFACE
................................................................................................................................... 4
R
ECEIVE
I
NTERFACE
..................................................................................................................................... 6
C
LOCK
I
NTERFACE
........................................................................................................................................ 8
CONTROL AND ALARM INTERFACE ....................................................................................................... 9
A
NALOG
P
OWER
AND
G
ROUND
................................................................................................................... 12
DIGITAL
P
OWER
AND
G
ROUND
..................................................................................................................... 14
FUNCTIONAL DESCRIPTION ......................................................................................... 16
1.0 R3 Technology (reconfigurable, relayless redundancy) ............................................................... 16
1.1 N
ETWORK
A
RCHITECTURE
................................................................................................................................ 16
Figure 3. Network Redundancy Architecture ................................................................................................. 16
2.0 clock Synthesizer ............................................................................................................................. 17
2.1 C
LOCK
D
ISTRIBUTION
....................................................................................................................................... 17
Figure 5. Clock Distribution Congifured in E3 Mode Without Using SFM ....................................................... 17
Figure 4. Simplified Block Diagram of the Input Clock Circuitry Driving the Microprocessor .......................... 17
3.0 The Receiver Section ....................................................................................................................... 18
Figure 6. Receive Path Block Diagram ........................................................................................................... 18
3.1 R
ECEIVE
L
INE
I
NTERFACE
................................................................................................................................. 18
Figure 7. Receive Line InterfaceConnection ................................................................................................... 18
3.2 A
DAPTIVE
G
AIN
C
ONTROL
(AGC) ..................................................................................................................... 19
3.3 R
ECEIVE
E
QUALIZER
........................................................................................................................................ 19
Figure 8. ACG/Equalizer Block Diagram ......................................................................................................... 19
3.3.1 Recommendations for Equalizer Settings ....................................................................................... 19
3.4 C
LOCK
AND
D
ATA
R
ECOVERY
.......................................................................................................................... 19
3.4.1 Data/Clock Recovery Mode ............................................................................................................... 19
3.4.2 Training Mode ..................................................................................................................................... 19
3.5 LOS (L
OSS
OF
S
IGNAL
) D
ETECTOR
.................................................................................................................. 20
3.5.1 DS3/STS-1 LOS Condition ................................................................................................................. 20
3.5.2 Disabling ALOS/DLOS Detection ...................................................................................................... 20
T
ABLE
1: T
HE
ALOS (A
NALOG
LOS) D
ECLARATION
AND
C
LEARANCE
T
HRESHOLDS
FOR
A
GIVEN
SETTING
OF
LOSTHR
AND
REQEN (DS3
AND
STS-1 A
PPLICATIONS
) ................................................................... 20
3.5.3 E3 LOS Condition: ............................................................................................................................. 21
Figure 9. Loss Of Signal Definition for E3 as per ITU-T G.775 ....................................................................... 21
Figure 10. Loss of Signal Definition for E3 as per ITU-T G.775. ..................................................................... 21
3.5.4 Interference Tolerance ....................................................................................................................... 22
Figure 11. Interference Margin Test Set up for DS3/STS-1 ............................................................................ 22
Figure 12. Interference Margin Test Set up for E3. ......................................................................................... 22
T
ABLE
2: I
NTERFERENCE
M
ARGIN
T
EST
R
ESULTS
.............................................................................................. 23
3.5.5 Muting the Recovered Data with LOS condition: ............................................................................ 24
3.6 B3ZS/HDB3 D
ECODER
.................................................................................................................................... 24
Figure 13. Receiver Data output and code violation timing ............................................................................ 24
4.0 The Transmitter Section .................................................................................................................. 25
Figure 14. Transmit Path Block Diagram ........................................................................................................ 25
4.1 T
RANSMIT
D
IGITAL
I
NPUT
I
NTERFACE
................................................................................................................ 25
相關PDF資料
PDF描述
XRT75R06 SIX CHANNEL E3/DS3/STS-1 LINE INTERFACE UNIT WITH JITTER ATTENUATOR
XRT75R06IB SIX CHANNEL E3/DS3/STS-1 LINE INTERFACE UNIT WITH JITTER ATTENUATOR
XRT75R12D TWELVE CHANNEL E3/DS3/STS-1 LINE INTERFACE UNIT WITH SONET DESYNCHRONIZER
XRT75R12DIB TWELVE CHANNEL E3/DS3/STS-1 LINE INTERFACE UNIT WITH SONET DESYNCHRONIZER
XRT75R12 TWELVE CHANNEL E3/DS3/STS-1 LINE INTERFACE UNIT WITH JITTER ATTENUATOR
相關代理商/技術參數(shù)
參數(shù)描述
XRT75R06DIB-F 功能描述:網(wǎng)絡控制器與處理器 IC 6 Channel 3.3V-5V temp -45 to 85C RoHS:否 制造商:Micrel 產(chǎn)品:Controller Area Network (CAN) 收發(fā)器數(shù)量: 數(shù)據(jù)速率: 電源電流（最大值）:595 mA 最大工作溫度:+ 85 C 安裝風格:SMD/SMT 封裝 / 箱體:PBGA-400 封裝:Tray
XRT75R06ES 功能描述:時鐘合成器/抖動清除器 6CH T3/E3/STS1LIU+JA 3.3V W/REDUNDANCY RoHS:否 制造商:Skyworks Solutions, Inc. 輸出端數(shù)量: 輸出電平: 最大輸出頻率: 輸入電平: 最大輸入頻率:6.1 GHz 電源電壓-最大:3.3 V 電源電壓-最小:2.7 V 封裝 / 箱體:TSSOP-28 封裝:Reel
XRT75R06IB 功能描述:外圍驅(qū)動器與原件 - PCI 6CH E3/DS3/STS1 LIU+Jitter Attenuato RoHS:否 制造商:PLX Technology 工作電源電壓: 最大工作溫度: 安裝風格:SMD/SMT 封裝 / 箱體:FCBGA-1156 封裝:Tray
XRT75R06IB208 制造商:Exar Corporation 功能描述:Line Interface Unit 51.84Mbps DS3/E3/STS-1 Parallel 217-Pin BGA
XRT75R06IB-F 功能描述:外圍驅(qū)動器與原件 - PCI 6 Channel 3.3V-5V temp -45 to 85C RoHS:否 制造商:PLX Technology 工作電源電壓: 最大工作溫度: 安裝風格:SMD/SMT 封裝 / 箱體:FCBGA-1156 封裝:Tray
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