參數(shù)資料
型號: XRT75R06DIB
廠商: EXAR CORP
元件分類: 數(shù)字傳輸電路
英文描述: SIX CHANNEL E3/DS3/STS-1 LINE INTERFACE UNIT WITH SONET DESYNCHRONIZER
中文描述: DATACOM, PCM TRANSCEIVER, PBGA217
封裝: 23 X 23 MM, BGA-217
文件頁數(shù): 91/105頁
文件大?。?/td> 591K
代理商: XRT75R06DIB
á
SIX CHANNEL E3/DS3/STS-1 LINE INTERFACE UNIT WITH SONET DESYNCHRONIZER
XRT75R06D
REV. 1.0.0
86
8.7.2
Wander Measurement test results will be provided in the next revision of the LIU Data Sheet.
8.8
Designing with the LIU
In this section, we will discuss the following topics.
How to design with and configure the LIU to permit a system to meet the above-mentioned Intrinsic Jitter and
Wander requirements.
How is the LIU able to meet the above-mentioned requirements
How does the LIU permits the user to comply with the SONET APS Recovery Time requirements of 50ms
(per Telcordia GR-253-CORE)
How should one configure the LIU, if one needs to support "Daisy-Chain" Testing at the end Customer's site
8.8.1
How to design and configure the LIU to permit a system to meet the above-mentioned
Intrinsic Jitter and Wander requirements
As mentioned earlier, in most application (in which the LIU will be used in a SONET De-Sync Application) the
user will typically interface the LIU to a Mapper device in the manner as presented below in Figure 66.
In this application, the Mapper has the responsibility of receiving a SONET STS-N/OC-N signal and extracting
as many as N DS3 signals from this signal. As a given channel within the Mapper IC extracts out a given DS3
signal (from SONET) it will typically be applying a Clock and Data signal to the "Transmit Input" of the LIU IC.
Figure 66 presents a simple illustration as to how one channel, within the LIU should be connected to the
Mapper IC.
Wander Measurement Test Results
As mentioned above, the Mapper IC will typically output a Clock and Data signal to the LIU. In many cases,
the Mapper IC will output the contents of an entire STS-1 data-stream via the Data Signal to the LIU. However,
the Mapper IC typically only supplies a clock pulse via the Clock Signal to the LIU coincident to whenever a
DS3 bit is being output via the Data Signal. In this case, the Mapper IC would not supply a clock edge
coincident to when a TOH, POH or any non-DS3 data-bit is being output via the Data-Signal.
Figure 66 indicates that the Data Signal from the Mapper device should be connected to the TPDATA_n input
pin of the LIU IC and that the Clock Signal from the Mapper device should be connected to the TCLK_n input
pin of the LIU IC.
In this application, the LIU has the following responsibilities.
F
IGURE
66. I
LLUSTRATION
OF
THE
LIU
BEING
CONNECTED
TO
A
M
APPER
IC
FOR
SONET D
E
-S
YNC
A
PPLICATIONS
IC
DS3 to STS-N
Mapper/
Demapper
LIU
STS-N Signal
TPDATA_n input pin
TCLK n input
De-Mapped (Gapped)
DS3 Data and Clock
相關(guān)PDF資料
PDF描述
XRT75R06 SIX CHANNEL E3/DS3/STS-1 LINE INTERFACE UNIT WITH JITTER ATTENUATOR
XRT75R06IB SIX CHANNEL E3/DS3/STS-1 LINE INTERFACE UNIT WITH JITTER ATTENUATOR
XRT75R12D TWELVE CHANNEL E3/DS3/STS-1 LINE INTERFACE UNIT WITH SONET DESYNCHRONIZER
XRT75R12DIB TWELVE CHANNEL E3/DS3/STS-1 LINE INTERFACE UNIT WITH SONET DESYNCHRONIZER
XRT75R12 TWELVE CHANNEL E3/DS3/STS-1 LINE INTERFACE UNIT WITH JITTER ATTENUATOR
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