參數資料
型號： XRT75R06DIB
廠商： EXAR CORP
元件分類： 數字傳輸電路
英文描述： SIX CHANNEL E3/DS3/STS-1 LINE INTERFACE UNIT WITH SONET DESYNCHRONIZER
中文描述： DATACOM, PCM TRANSCEIVER, PBGA217
封裝： 23 X 23 MM, BGA-217
文件頁數： 5/105頁
文件大小： 591K
代理商： XRT75R06DIB
á
REV. 1.0.0
XRT75R06D
SIX CHANNEL E3/DS3/STS-1 LINE INTERFACE UNIT WITH SONET DESYNCHRONIZER
II
Figure 15. Typical interface between terminal equipment and the XRT75R06D (dual-rail data) ................... 25
Figure 16. Transmitter Terminal Input Timing ................................................................................................ 26
Figure 17. Single-Rail or NRZ Data Format (Encoder and Decoder are Enabled) ......................................... 26
4.2 T
RANSMIT
C
LOCK
............................................................................................................................................ 27
4.3 B3ZS/HDB3 E
NCODER
................................................................................................................................... 27
4.3.1 B3ZS Encoding .................................................................................................................................. 27
4.3.2 HDB3 Encoding .................................................................................................................................. 27
Figure 18. Dual-Rail Data Format (encoder and decoder are disabled) ......................................................... 27
Figure 19. B3ZS Encoding Format ................................................................................................................. 27
4.4 T
RANSMIT
P
ULSE
S
HAPER
............................................................................................................................... 28
Figure 21. Transmit Pulse Shape Test Circuit ................................................................................................ 28
4.4.1 Guidelines for using Transmit Build Out Circuit ............................................................................. 28
Figure 20. HDB3 Encoding Format ................................................................................................................ 28
4.5 E3
LINE
SIDE
PARAMETERS
.............................................................................................................................. 29
Figure 22. Pulse Mask for E3 (34.368 mbits/s) interface as per itu-t G.703 ................................................... 29
T
ABLE
3: E3 T
RANSMITTER
LINE
SIDE
OUTPUT
AND
RECEIVER
LINE
SIDE
INPUT
SPECIFICATIONS
.......................... 30
Figure 23. Bellcore GR-253 CORE Transmit Output Pulse Template for SONET STS-1 Applications ......... 31
T
ABLE
4: STS-1 P
ULSE
M
ASK
E
QUATIONS
........................................................................................................ 31
T
ABLE
5: STS-1 T
RANSMITTER
L
INE
S
IDE
O
UTPUT
AND
R
ECEIVER
L
INE
S
IDE
I
NPUT
S
PECIFICATIONS
(GR-253) . 32
Figure 24. Transmit Ouput Pulse Template for DS3 as per Bellcore GR-499 ................................................ 32
T
ABLE
7: DS3 T
RANSMITTER
L
INE
S
IDE
O
UTPUT
AND
R
ECEIVER
L
INE
S
IDE
I
NPUT
S
PECIFICATIONS
(GR-499) .... 33
T
ABLE
6: DS3 P
ULSE
M
ASK
E
QUATIONS
........................................................................................................... 33
4.6 T
RANSMIT
D
RIVE
M
ONITOR
.............................................................................................................................. 34
4.7 T
RANSMITTER
S
ECTION
O
N
/O
FF
....................................................................................................................... 34
Figure 25. Transmit Driver Monitor set-up. ..................................................................................................... 34
5.0 Jitter .................................................................................................................................................. 35
5.1 J
ITTER
T
OLERANCE
.......................................................................................................................................... 35
5.1.1 DS3/STS-1 Jitter Tolerance Requirements ...................................................................................... 35
Figure 26. Jitter Tolerance Measurements ..................................................................................................... 35
5.1.2 E3 Jitter Tolerance Requirements .................................................................................................... 36
Figure 27. Input Jitter Tolerance For DS3/STS-1 .......................................................................................... 36
Figure 28. Input Jitter Tolerance for E3 ......................................................................................................... 36
5.2 J
ITTER
T
RANSFER
............................................................................................................................................ 37
5.3 J
ITTER
A
TTENUATOR
........................................................................................................................................ 37
T
ABLE
8: J
ITTER
A
MPLITUDE
VERSUS
M
ODULATION
F
REQUENCY
(J
ITTER
T
OLERANCE
) ....................................... 37
T
ABLE
9: J
ITTER
T
RANSFER
S
PECIFICATION
/R
EFERENCES
................................................................................. 37
5.3.1 Jitter Generation ................................................................................................................................ 38
T
ABLE
10: J
ITTER
T
RANSFER
P
ASS
M
ASKS
....................................................................................................... 38
Figure 29. Jitter Transfer Requirements and Jitter Attenuator Performance .................................................. 38
6.0 Diagnostic Features ......................................................................................................................... 39
6.1 PRBS G
ENERATOR
AND
D
ETECTOR
................................................................................................................. 39
Figure 30. PRBS MODE ................................................................................................................................. 39
6.2 LOOPBACKS ................................................................................................................................................ 40
6.2.1 ANALOG LOOPBACK ........................................................................................................................ 40
Figure 31. Analog Loopback ........................................................................................................................... 40
6.2.2 DIGITAL LOOPBACK ......................................................................................................................... 41
6.2.3 REMOTE LOOPBACK ........................................................................................................................ 41
Figure 32. Digital Loopback ............................................................................................................................ 41
Figure 33. Remote Loopback ......................................................................................................................... 41
6.3 TRANSMIT ALL ONES (TAOS) .................................................................................................................... 42
Figure 34. Transmit All Ones (TAOS) ............................................................................................................. 42
7.0 Microprocessor interface Block ..................................................................................................... 43
T
ABLE
11: S
ELECTING
THE
M
ICROPROCESSOR
I
NTERFACE
M
ODE
...................................................................... 43
Figure 35. Simplified Block Diagram of the Microprocessor Interface Block .................................................. 43
7.1 T
HE
M
ICROPROCESSOR
I
NTERFACE
B
LOCK
S
IGNALS
........................................................................................ 44
T
ABLE
12: XRT75R06D M
ICROPROCESSOR
I
NTERFACE
S
IGNALS
...................................................................... 44
相關PDF資料
PDF描述
XRT75R06 SIX CHANNEL E3/DS3/STS-1 LINE INTERFACE UNIT WITH JITTER ATTENUATOR
XRT75R06IB SIX CHANNEL E3/DS3/STS-1 LINE INTERFACE UNIT WITH JITTER ATTENUATOR
XRT75R12D TWELVE CHANNEL E3/DS3/STS-1 LINE INTERFACE UNIT WITH SONET DESYNCHRONIZER
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XRT75R12 TWELVE CHANNEL E3/DS3/STS-1 LINE INTERFACE UNIT WITH JITTER ATTENUATOR
相關代理商/技術參數
參數描述
XRT75R06DIB-F 功能描述:網絡控制器與處理器 IC 6 Channel 3.3V-5V temp -45 to 85C RoHS:否 制造商:Micrel 產品:Controller Area Network (CAN) 收發(fā)器數量: 數據速率: 電源電流（最大值）:595 mA 最大工作溫度:+ 85 C 安裝風格:SMD/SMT 封裝 / 箱體:PBGA-400 封裝:Tray
XRT75R06ES 功能描述:時鐘合成器/抖動清除器 6CH T3/E3/STS1LIU+JA 3.3V W/REDUNDANCY RoHS:否 制造商:Skyworks Solutions, Inc. 輸出端數量: 輸出電平: 最大輸出頻率: 輸入電平: 最大輸入頻率:6.1 GHz 電源電壓-最大:3.3 V 電源電壓-最小:2.7 V 封裝 / 箱體:TSSOP-28 封裝:Reel
XRT75R06IB 功能描述:外圍驅動器與原件 - PCI 6CH E3/DS3/STS1 LIU+Jitter Attenuato RoHS:否 制造商:PLX Technology 工作電源電壓: 最大工作溫度: 安裝風格:SMD/SMT 封裝 / 箱體:FCBGA-1156 封裝:Tray
XRT75R06IB208 制造商:Exar Corporation 功能描述:Line Interface Unit 51.84Mbps DS3/E3/STS-1 Parallel 217-Pin BGA
XRT75R06IB-F 功能描述:外圍驅動器與原件 - PCI 6 Channel 3.3V-5V temp -45 to 85C RoHS:否 制造商:PLX Technology 工作電源電壓: 最大工作溫度: 安裝風格:SMD/SMT 封裝 / 箱體:FCBGA-1156 封裝:Tray
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