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參數(shù)資料
| 型號(hào)： | XRT75R06DIB |
| 廠商： | EXAR CORP |
| 元件分類： | 數(shù)字傳輸電路 |
| 英文描述： | SIX CHANNEL E3/DS3/STS-1 LINE INTERFACE UNIT WITH SONET DESYNCHRONIZER |
| 中文描述： | DATACOM, PCM TRANSCEIVER, PBGA217 |
| 封裝： | 23 X 23 MM, BGA-217 |
| 文件頁(yè)數(shù)： | 57/105頁(yè) |
| 文件大小： | 591K |
| 代理商： | XRT75R06DIB |
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SIX CHANNEL E3/DS3/STS-1 LINE INTERFACE UNIT WITH SONET DESYNCHRONIZER
XRT75R06D
REV. 1.0.0
52
T
ABLE
18: R
EGISTER
M
AP
D
ESCRIPTION
- C
HANNEL
N
A
DDRESS
(H
EX
)
T
YPE
R
EGISTER
N
AME
BIT#
S
YMBOL
D
ESCRIPTION
D
EFAULT
V
ALUE
0x01 (ch 0)
0x11 (ch 1)
0x21 (ch 2)
0x31 (ch 3)
0x41 (ch 4)
0x51 (ch 5)
R/W
Interrupt
Enable
(source
level)
D0
DMOIE_n
If the Driver Monitor (connected to the output of the
channel) detects the absence of pulses for 128 con-
secutive cycles, it will set the interrupt flag if this bit
has been set.
0
D1
RLOSIE_n This flag will allow a loss of receive signal(for that
channel) to send an interrupt to the Host when this
bit is set.
0
D2
RLOLIE_n
This flag will allow a loss of lock condition to send an
interrupt to the Host when this bit is set.
0
D3
FLIE_n
Set this bit to enable the interrupt when the FIFO
Limit of the Jitter Attenuator is within 2 bits of over-
flow/underflow condition.
N
OTE
:
This bit field is ignored when the Jitter Atten-
uator is disabled.
0
D4
PRBSERIE
_n
Set this bit to enable the interrupt when the PRBS
error is detected.
0
D5
PRBSERC
NTIE_n
Set this bit to enable the interrupt when the PRBS
error count register saturates.
0
D6-D7
Reserved
0x02 (ch 0)
0x12 (ch 1)
0x22 (ch 2)
0x32 (ch 3)
0x42 (ch 4)
0x52 (ch 5)
Reset
on
Read
Interrupt
Status
(source
level)
D0
DMOIS_n
If the Drive monitor circuot detects the absence of
pulses for 128 consecutive cycles, t will set this
interrupt status flag (if enabled) This bit is set on a
change of state of the DMO circuit.
0
D1
RLOSIS_n This flag will indicate a change of “l(fā)oss of Receive
signal” to the Host when this bit is set.
0
D2
RLOLIS_n
This flag will allow a change in the loss of lock condi-
tion to send an interrupt to the Host when this bit is
enabled.Loss of lock is defined as a difference of
greater than 0.5% between the recovered clock and
the channel’s reference clock. Any change (return to
lock) will trigger the interrupt status flag again.
0
D3
FLIS_n
This bit will generate an interrupt if the jitter attenua-
tor FIFO reaches (or leaves) a limit condition. This
limit condition is defined as the FIFO being within
two counts of full or empty.
0
D4
PRBSERIS
_n
This bit is set when the PRBS error occurs.
0
D5
PRBSERC
NTIS_n
This bit is set when the PRBS error count register
saturates.
0
D7-D6
Reserved
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| XRT75R06 | SIX CHANNEL E3/DS3/STS-1 LINE INTERFACE UNIT WITH JITTER ATTENUATOR |
| XRT75R06IB | SIX CHANNEL E3/DS3/STS-1 LINE INTERFACE UNIT WITH JITTER ATTENUATOR |
| XRT75R12D | TWELVE CHANNEL E3/DS3/STS-1 LINE INTERFACE UNIT WITH SONET DESYNCHRONIZER |
| XRT75R12DIB | TWELVE CHANNEL E3/DS3/STS-1 LINE INTERFACE UNIT WITH SONET DESYNCHRONIZER |
| XRT75R12 | TWELVE CHANNEL E3/DS3/STS-1 LINE INTERFACE UNIT WITH JITTER ATTENUATOR |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| XRT75R06DIB-F | 功能描述:網(wǎng)絡(luò)控制器與處理器 IC 6 Channel 3.3V-5V temp -45 to 85C RoHS:否 制造商:Micrel 產(chǎn)品:Controller Area Network (CAN) 收發(fā)器數(shù)量: 數(shù)據(jù)速率: 電源電流（最大值）:595 mA 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:PBGA-400 封裝:Tray |
| XRT75R06ES | 功能描述:時(shí)鐘合成器/抖動(dòng)清除器 6CH T3/E3/STS1LIU+JA 3.3V W/REDUNDANCY RoHS:否 制造商:Skyworks Solutions, Inc. 輸出端數(shù)量: 輸出電平: 最大輸出頻率: 輸入電平: 最大輸入頻率:6.1 GHz 電源電壓-最大:3.3 V 電源電壓-最小:2.7 V 封裝 / 箱體:TSSOP-28 封裝:Reel |
| XRT75R06IB | 功能描述:外圍驅(qū)動(dòng)器與原件 - PCI 6CH E3/DS3/STS1 LIU+Jitter Attenuato RoHS:否 制造商:PLX Technology 工作電源電壓: 最大工作溫度: 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FCBGA-1156 封裝:Tray |
| XRT75R06IB208 | 制造商:Exar Corporation 功能描述:Line Interface Unit 51.84Mbps DS3/E3/STS-1 Parallel 217-Pin BGA |
| XRT75R06IB-F | 功能描述:外圍驅(qū)動(dòng)器與原件 - PCI 6 Channel 3.3V-5V temp -45 to 85C RoHS:否 制造商:PLX Technology 工作電源電壓: 最大工作溫度: 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FCBGA-1156 封裝:Tray |
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