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參數資料
| 型號： | XRT83SL34IV-F |
| 廠商： | Exar Corporation |
| 文件頁數： | 15/80頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC LIU T1/E1/J1 QUAD 128TQFP |
| 標準包裝： | 72 |
| 類型： | 線路接口裝置（LIU） |
| 驅動器/接收器數： | 4/4 |
| 規(guī)程： | T1，E1，J1 |
| 電源電壓： | 3.135 V ~ 3.465 V |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 128-LQFP |
| 供應商設備封裝： | 128-TQFP（14x20） |
| 包裝： | 托盤 |
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XRT83SL34
QUAD T1/E1/J1 SH TRANSCEIVER WITH CLOCK RECOVERY AND JITTER ATTENUATOR
REV. 1.0.0
19
In Host mode the programming is achieved through the corresponding interface control bits, the state of the
CLKSEL[2:0] control bits and the state of the MCLKRATE interface control bit.
RECEIVER
In Hardware mode all receive channels are turned on upon power-up and there is no provision supplied to
power them off. In Host mode, each receiver channel can be individually powered on or off with its respective
channel RXON_n bit. See “Microprocessor Register #0, Bit Description” on page 45.
RECEIVER INPUT
At the receiver input, a cable attenuated AMI signal can be coupled to the receiver through a capacitor or a 1:1
transformer. The input signal is first applied to a selective equalizer for signal conditioning. The maximum
equalizer gain is up to 36 dB for both T1 and E1 modes. The equalized signal is subsequently applied to a
peak detector which in turn controls the equalizer settings and the data slicer. The slicer threshold for both E1
and T1 is typically set at 50% of the peak amplitude at the equalizer output. After the slicers, the digital
representation of the AMI signals are applied to the clock and data recovery circuit. The recovered data
subsequently goes through the jitter attenuator and decoder (if selected) for HDB3 or B8ZS decoding before
being applied to the RPOS_n/RDATA_n and RNEG_n/LCV_n pins. Clock recovery is accomplished by a digital
phase-locked loop (DPLL) which does not require any external components and can tolerate high levels of
input jitter that meets or exceeds the ITU-G.823 and TR-TSY000499 standards.
TABLE 1: MASTER CLOCK GENERATOR
MCLKE1
K
HZ
MCLKT1
K
HZ
CLKSEL2
CLKSEL1
CLKSEL0
MCLKRATE
MASTER CLOCK
K
HZ
2048
0
2048
0
1
1544
2048
1544
0
2048
1544
0
1
1544
0
1
0
2048
1544
0
1
1544
8
x
01
00
2048
8
x
01
1544
16
x
0
1
0
2048
16
x
0
1
1544
56
x
1
0
2048
56
x
1
0
1
1544
64
x
1
0
1
0
2048
64
x
1
0
1
1544
128
x
11
00
2048
128
x
11
01
1544
256
x
11
10
2048
256
x
11
1544
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