- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄2121 > XRT83SL34IV-F (Exar Corporation)IC LIU T1/E1/J1 QUAD 128TQFP PDF資料下載
參數(shù)資料
| 型號： | XRT83SL34IV-F |
| 廠商： | Exar Corporation |
| 文件頁數(shù)： | 17/80頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC LIU T1/E1/J1 QUAD 128TQFP |
| 標(biāo)準(zhǔn)包裝： | 72 |
| 類型： | 線路接口裝置（LIU） |
| 驅(qū)動器/接收器數(shù)： | 4/4 |
| 規(guī)程： | T1，E1，J1 |
| 電源電壓： | 3.135 V ~ 3.465 V |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 128-LQFP |
| 供應(yīng)商設(shè)備封裝： | 128-TQFP（14x20） |
| 包裝： | 托盤 |
第1頁第2頁第3頁第4頁第5頁第6頁第7頁第8頁第9頁第10頁第11頁第12頁第13頁第14頁第15頁第16頁當(dāng)前第17頁第18頁第19頁第20頁第21頁第22頁第23頁第24頁第25頁第26頁第27頁第28頁第29頁第30頁第31頁第32頁第33頁第34頁第35頁第36頁第37頁第38頁第39頁第40頁第41頁第42頁第43頁第44頁第45頁第46頁第47頁第48頁第49頁第50頁第51頁第52頁第53頁第54頁第55頁第56頁第57頁第58頁第59頁第60頁第61頁第62頁第63頁第64頁第65頁第66頁第67頁第68頁第69頁第70頁第71頁第72頁第73頁第74頁第75頁第76頁第77頁第78頁第79頁第80頁
XRT83SL34
QUAD T1/E1/J1 SH TRANSCEIVER WITH CLOCK RECOVERY AND JITTER ATTENUATOR
REV. 1.0.0
21
typically -38dB (-29dB + -9dB). A 3dB hysteresis was designed so that transients will not trigger the RLOS to
clear. Therefore, the RLOS will typically clear at a total flat loss of -35dB. See Figure 7 for a simplified diagram.
RECEIVE HDB3/B8ZS DECODER
The Decoder function is available in both Hardware and Host modes on a per channel basis by controlling the
TNEG_n/CODES_n pin or the CODES_n interface bit. The decoder function is only active in single-rail Mode.
When selected, receive data in this mode will be decoded according to HDB3 rules for E1 and B8ZS for T1
systems. Bipolar violations that do not conform to the coding scheme will be reported as Line Code Violation at
the RNEG_n/LCV_n pin of each channel. The length of the LCV pulse is one RCLK cycle for each code
violation. In E1mode only, an excessive number of zeros in the receive data stream is also reported as an error
at the same output pin. If AMI decoding is selected in single rail mode, every bipolar violation in the receive
data stream will be reported as an error at the RNEG_n/LCV_n pin.
RECOVERED CLOCK (RCLK) SAMPLING EDGE
This feature is available in both Hardware and Host modes on a global basis. In Host mode, the sampling
edge of RCLK output can be changed through the interface control bit RCLKE. If a “1” is written in the RCLKE
interface bit, receive data output at RPOS_n/RDATA_n and RNEG_n/LCV_n are updated on the falling edge of
RCLK for all eight channels. Writing a “0” to the RCLKE register, updates the receive data on the rising edge of
RCLK. In Hardware mode the same feature is available under the control of the RCLKE pin.
FIGURE 7. SIMPLIFIED DIAGRAM OF -29dB T1/E1 GAIN MODE AND RLOS CONDITION
FIGURE 8. RECEIVE CLOCK AND OUTPUT DATA TIMING
Norm alized up to +29dB Max
Declare LOS
Clear LOS
-9dB
+3dB
Clear LOS
Declare LOS
+3dB
-9dB
RCLK
R
RCLK
F
RCLK
RPOS
or
RNEG
R
DY
R
HO
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| XRT83SL38IB-F | IC LIU SH T1/E1/J1 OCTAL 225BGA |
| XRT83VL38IB-F | IC LIU SH T1/E1/J1 OCTAL 225BGA |
| XRT83VSH28IB | IC LIU SH E1 OCTAL 225BGA |
| XRT83VSH314IB-F | IC LIU SH T1/E1/J1 14CH 304TBGA |
| XRT83VSH316IB | IC LIU SH T1/E1/J1 16CH 316STBGA |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| XRT83SL38 | 制造商:EXAR 制造商全稱:EXAR 功能描述:OCTAL T1/E1/J1 SH TRANSCEIVER WITH CLOCK RECOVERY AND JITTER ATTENUATOR |
| XRT83SL38_07 | 制造商:EXAR 制造商全稱:EXAR 功能描述:OCTAL T1/E1/J1 SH TRANSCEIVER WITH CLOCK RECOVERY AND JITTER |
| XRT83SL38ES | 功能描述:外圍驅(qū)動器與原件 - PCI 8 CHT1/E1LIUSH RoHS:否 制造商:PLX Technology 工作電源電壓: 最大工作溫度: 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FCBGA-1156 封裝:Tray |
| XRT83SL38ES-BG | 功能描述:界面開發(fā)工具 Eval System for XRT83SL38 Series RoHS:否 制造商:Bourns 產(chǎn)品:Evaluation Boards 類型:RS-485 工具用于評估:ADM3485E 接口類型:RS-485 工作電源電壓:3.3 V |
| XRT83SL38IB | 功能描述:時鐘合成器/抖動清除器 RoHS:否 制造商:Skyworks Solutions, Inc. 輸出端數(shù)量: 輸出電平: 最大輸出頻率: 輸入電平: 最大輸入頻率:6.1 GHz 電源電壓-最大:3.3 V 電源電壓-最小:2.7 V 封裝 / 箱體:TSSOP-28 封裝:Reel |
發(fā)布緊急采購，3分鐘左右您將得到回復(fù)。