TABLE
參數(shù)資料
型號: XRT83SL34IV-F
廠商: Exar Corporation
文件頁數(shù): 57/80頁
文件大?。?/td> 0K
描述: IC LIU T1/E1/J1 QUAD 128TQFP
標準包裝: 72
類型: 線路接口裝置(LIU)
驅(qū)動器/接收器數(shù): 4/4
規(guī)程: T1,E1,J1
電源電壓: 3.135 V ~ 3.465 V
安裝類型: 表面貼裝
封裝/外殼: 128-LQFP
供應(yīng)商設(shè)備封裝: 128-TQFP(14x20)
包裝: 托盤
XRT83SL34
QUAD T1/E1/J1 SH TRANSCEIVER WITH CLOCK RECOVERY AND JITTER ATTENUATOR
REV. 1.0.0
57
TABLE 27: MICROPROCESSOR REGISTER #8, BIT DESCRIPTION
REGISTER ADDRESS
0001000
0011000
0101000
0111000
CHANNEL_n
CHANNEL_0
CHANNEL_1
CHANNEL_2
CHANNEL_3
FUNCTION
REGISTER
TYPE
RESET
VALUE
BIT #NAME
D7
Reserved
R/W
0
D6-D0
B6S1_n -
B0S1_n
Arbitrary Transmit Pulse Shape, Segment 1:The shape of
each channel’s transmitted pulse can be made independently
user programmable by selecting “Arbitrary Pulse” mode in
Table 5. The arbitrary pulse is divided into eight time seg-
ments whose combined duration is equal to one period of
MCLK.
This 7 bit number represents the amplitude of the nth chan-
nel's arbitrary pulse during the first time segment. B6S1_n-
B0S1_n is in signed magnitude format with B6S1_n as the
sign bit and B0S1_n as the least significant bit (LSB).
R/W
0
TABLE 28: MICROPROCESSOR REGISTER #9, BIT DESCRIPTION
REGISTER ADDRESS
0001001
0011001
0101001
0111001
CHANNEL_n
CHANNEL_0
CHANNEL_1
CHANNEL_2
CHANNEL_3
FUNCTION
REGISTER
TYPE
RESET
VALUE
BIT #NAME
D7
Reserved
R/W
0
D6-D0
B6S2_n -
B0S2_n
Arbitrary Transmit Pulse Shape, Segment 2
The shape of each channel's transmitted pulse can be made
independently user programmable by selecting “Arbitrary
Pulse” mode in
Table 5. The arbitrary pulse is divided into
eight time segments whose combined duration is equal to one
period of MCLK.
This 7 bit number represents the amplitude of the nth chan-
nel's arbitrary pulse during the second time segment. B6S2_n-
B0S2_n is in signed magnitude format with B6S2_n as the
sign bit and B0S2_n as the least significant bit (LSB).
R/W
0
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