參數(shù)資料
型號(hào)： XRT83SL34IV-F
廠商： Exar Corporation
文件頁數(shù)： 21/80頁
文件大?。?/td> 0K
描述： IC LIU T1/E1/J1 QUAD 128TQFP
標(biāo)準(zhǔn)包裝： 72
類型： 線路接口裝置（LIU）
驅(qū)動(dòng)器/接收器數(shù)： 4/4
規(guī)程： T1，E1，J1
電源電壓： 3.135 V ~ 3.465 V
安裝類型： 表面貼裝
封裝/外殼： 128-LQFP
供應(yīng)商設(shè)備封裝： 128-TQFP（14x20）
包裝： 托盤
XRT83SL34
QUAD T1/E1/J1 SH TRANSCEIVER WITH CLOCK RECOVERY AND JITTER ATTENUATOR
REV. 1.0.0
25
DRIVER FAILURE MONITOR (DMO)
The driver monitor circuit is used to detect transmit driver failure by monitoring the activities at TTIP and TRING
outputs. Driver failure may be caused by a short circuit in the primary transformer or system problems at the
transmit input. If the transmitter of a channel has no output for more than 128 clock cycles, the corresponding
DMO pin goes “High” and remains “High” until a valid transmit pulse is detected. In Host mode, the failure of
the transmit channel is reported in the corresponding interface bit. If the DMOIE bit is also enabled, any
transition on the DMO interface bit will generate an interrupt. The driver failure monitor is supported in both
Hardware and Host modes on a per channel basis.
TRANSMIT PULSE SHAPER & LINE BUILD OUT (LBO) CIRCUIT
The transmit pulse shaper circuit uses the high speed clock from the Master timing generator to control the
shape and width of the transmitted pulse. The internal high-speed timing generator eliminates the need for a
tightly controlled transmit clock (TCLK) duty cycle. With the jitter attenuator not in the transmit path, the
transmit output will generate no more than 0.025Unit Interval (UI) peak-to-peak jitter. In Hardware mode, the
state of the A[4:0]/EQC[4:0] pins determine the transmit pulse shape for all eight channels. In Host mode
transmit pulse shape can be controlled on a per channel basis using the interface bits EQC[4:0]. The chip
supports five fixed transmit pulse settings for T1 Short-haul applications plus a fully programmable waveform
generator for arbitrary transmit output pulse shapes. The choice of the transmit pulse shape and LBO under
the control of the interface bits are summarized in Table 5. For CSU LBO transmit pulse design information,
refer to ANSI T1.403-1993 Network-to-Customer Installation specification, Annex-E.
NOTE:
EQC[4:0] determine the T1/E1 operating mode of the XRT83SL34. When EQC4 = “1” and EQC3 = “1”, the
XRT83SL34 is in the E1 mode, otherwise it is in the T1/J1 mode.
TABLE 5: RECEIVE EQUALIZER CONTROL AND TRANSMIT LINE BUILD-OUT SETTINGS
EQC4
EQC3
EQC2
EQC1
EQC0
E1/T1 MODE & RECEIVE
SENSITIVITY
TRANSMIT LBO
CABLE
CODING
0
1000
T1 Short Haul/15dB
0-133 ft./ 0.6dB
100
/ TP
B8ZS
0
1001
T1 Short Haul/15dB
133-266 ft./ 1.2dB
100
/ TP
B8ZS
0
1010
T1 Short Haul/15dB
266-399 ft./ 1.8dB
100
/ TP
B8ZS
0
1011
T1 Short Haul/15dB
399-533 ft./ 2.4dB
100
/ TP
B8ZS
0
1100
T1 Short Haul/15dB
533-655 ft./ 3.0dB
100
/ TP
B8ZS
0
1101
T1 Short Haul/15dB
Arbitrary Pulse
100
/ TP
B8ZS
0
1110
T1 Gain Mode/29dB
0-133 ft./ 0.6dB
100
/ TP
B8ZS
0
1111
T1 Gain Mode/29dB
133-266 ft./ 1.2dB
100
/ TP
B8ZS
1
0000
T1 Gain Mode/29dB
266-399 ft./ 1.8dB
100
/ TP
B8ZS
1
0001
T1 Gain Mode/29dB
399-533 ft./ 2.4dB
100
/ TP
B8ZS
1
0010
T1 Gain Mode/29dB
533-655 ft./ 3.0dB
100
/ TP
B8ZS
1
0011
T1 Gain Mode/29dB
Arbitrary Pulse
100
/ TP
B8ZS
1
1100
E1 Short Haul
ITU G.703
75
Coax
HDB3
1
1101
E1 Short Haul
ITU G.703
120
TP
HDB3
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