參數資料
| 型號： | XRT83SL34IV-F |
| 廠商： | Exar Corporation |
| 文件頁數： | 59/80頁 |
| 文件大小： | 0K |
| 描述： | IC LIU T1/E1/J1 QUAD 128TQFP |
| 標準包裝： | 72 |
| 類型： | 線路接口裝置（LIU） |
| 驅動器/接收器數： | 4/4 |
| 規(guī)程： | T1，E1，J1 |
| 電源電壓： | 3.135 V ~ 3.465 V |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 128-LQFP |
| 供應商設備封裝： | 128-TQFP（14x20） |
| 包裝： | 托盤 |
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XRT83SL34
QUAD T1/E1/J1 SH TRANSCEIVER WITH CLOCK RECOVERY AND JITTER ATTENUATOR
REV. 1.0.0
59
TABLE 31: MICROPROCESSOR REGISTER #12, BIT DESCRIPTION
REGISTER ADDRESS
0001100
0011100
0101100
0111100
CHANNEL_n
CHANNEL_0
CHANNEL_1
CHANNEL_2
CHANNEL_3
FUNCTION
REGISTER
TYPE
RESET
VALUE
BIT #NAME
D7
Reserved
R/W
0
D6-D0
B6S5_n -
B0S5_n
Arbitrary Transmit Pulse Shape, Segment 5
The shape of each channel’s transmitted pulse can be made
independently user programmable by selecting “Arbitrary
Pulse” mode in
Table 5. The arbitrary pulse is divided into
eight time segments whose combined duration is equal to one
period of MCLK.
This 7 bit number represents the amplitude of the nth chan-
nel's arbitrary pulse during the fifth time segment. B6S5_n-
B0S5_n is in signed magnitude format with B6S5_n as the
sign bit and B0S5_n as the least significant bit (LSB).
R/W
0
TABLE 32: MICROPROCESSOR REGISTER #13, BIT DESCRIPTION
REGISTER ADDRESS
0001101
0011101
0101101
0111101
CHANNEL_n
CHANNEL_0
CHANNEL_1
CHANNEL_2
CHANNEL_3
FUNCTION
REGISTER
TYPE
RESET
VALUE
BIT #NAME
D7
Reserved
R/W
0
D6-D0
B6S6_n -
B0S6_n
Arbitrary Transmit Pulse Shape, Segment 6
The shape of each channel's transmitted pulse can be made
independently user programmable by selecting “Arbitrary
Pulse” mode in
Table 5. The arbitrary pulse is divided into
eight time segments whose combined duration is equal to one
period of MCLK.
This 7 bit number represents the amplitude of the nth chan-
nel's arbitrary pulse during the sixth time segment. B6S6_n-
B0S6_n is in signed magnitude format with B6S6_n as the
sign bit and B0S6_n as the least significant bit (LSB).
R/W
0
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