參數(shù)資料
型號: XRT83SL34IV-F
廠商: Exar Corporation
文件頁數(shù): 78/80頁
文件大?。?/td> 0K
描述: IC LIU T1/E1/J1 QUAD 128TQFP
標準包裝: 72
類型: 線路接口裝置(LIU)
驅(qū)動器/接收器數(shù): 4/4
規(guī)程: T1,E1,J1
電源電壓: 3.135 V ~ 3.465 V
安裝類型: 表面貼裝
封裝/外殼: 128-LQFP
供應商設備封裝: 128-TQFP(14x20)
包裝: 托盤
XRT83SL34
QUAD T1/E1/J1 SH TRANSCEIVER WITH CLOCK RECOVERY AND JITTER ATTENUATOR
REV. 1.0.0
5
RRING_0
RRING_1
RRING_2
RRING_3
10
22
81
93
I
Receiver Differential Ring Negative Input for Channel _0
Negative differential receive input from the line.
Receiver Differential Ring Negative Input for Channel _1
Receiver Differential Ring Negative Input for Channel _2
Receiver Differential Ring Negative Input for Channel _3
RXMUTE
RDY_DTACK
73
I
O
Receive Muting - Hardware mode
Connecting this pin ‘High’ will mute (force to ground) the outputs RPOS_n/
RNEG_n when a LOS condition occurs, to prevent data chattering. This pin
is internally pulled "low" consequently muting is normally disabled.
NOTES:
1.
Internally pulled "Low" with 50k
resistor.
2.
In Hardware mode, all receive channels share the same RXMUTE
control function.
Ready Output (Data Transfer Acknowledge Output) - Host mode
RXRES0
RXRES1
108
109
I
Receive External Resistor Control Pins - Hardware mode
Receive External Resistor Control Pin 0
Receive External Resistor Control Pin 1
These pins are used to determine the value of the external Receive fixed
resistor according to the following table:
NOTE: These pins are internally pulled “Low” with 50k
resistor.
RCLKE
PTS1
106
I
Receive Clock Edge - Hardware Mode
Set this pin "High" to sample RPOS_N/RNEG_n on the falling edge of
RCLK_n. With this pin tied "Low", output data are updated on the rising edge
of RCLK_n.
Microprocessor Type Select Input pin 1 - Host mode
This pin along with PTS2 (pin 107) is used to select the microprocessor
NOTE: This pin is internally pulled "Low" with a 50k
resistor.
SIGNAL NAME
PIN #TYPE
DESCRIPTION
R equired Fixed External
RX Resistor
No External Fixed R esistor
240
210
150
RXRES0
0
1
0
1
RXRES 1
0
1
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