參數(shù)資料
型號: XRT83VL38IB-F
廠商: Exar Corporation
文件頁數(shù): 81/95頁
文件大?。?/td> 0K
描述: IC LIU SH T1/E1/J1 OCTAL 225BGA
標(biāo)準(zhǔn)包裝: 84
類型: 線路接口裝置(LIU)
驅(qū)動器/接收器數(shù): 8/8
規(guī)程: E1
電源電壓: 3.14 V ~ 3.47 V
安裝類型: 表面貼裝
封裝/外殼: 225-BGA
供應(yīng)商設(shè)備封裝: 225-BGA(19x19)
包裝: 托盤
其它名稱: 1016-1481
XRT83VL38IB-F-ND
XRT83VL38
78
OCTAL T1/E1/J1 LH/SH TRANSCEIVER WITH CLOCK RECOVERY AND JITTER ATTENUATOR
REV. 1.0.1
D3
SL_1
Slicer Level Control bit 1:
This bit and bit D2 control the slic-
ing level for the slicer per the following table.
R/W
0
D2
SL_0
Slicer Level Control bit 0:
See description bit D3.
R/W
0
D1
EQG_1
Equalizer Gain Control bit 1:
This bit together with bit D0
control the gain of the equalizer as shown in the table below.
R/W
0
D0
EQG_0
Equalizer Gain Control bit 0:
See description of bit D1
R/W
0
TABLE 43: MICROPROCESSOR REGISTER #192, BIT DESCRIPTION
REGISTER ADDRESS
11000000
NAME
FUNCTION
REGISTER
TYPE
RESET
VALUE
BIT #
D[7:1]
Reserved
These register bits are not used.
R/W
0
D0
E1Arben
E1 Arbitrary Pulse Enable
This bit is used to enable the Arbitrary Pulse Generators for
shaping the transmit pulse shape when E1 mode is selected.
If this bit is set to "1", all 8 channels will be configured for the
Arbitrary Mode. However, each channel is individually con-
trolled by programming the channel registers 0xn8 through
0xnF, where n is the number of the channel.
"0" = Disabled (Normal E1 Pulse Shape ITU G.703)
"1" = Arbitrary Pulse Enabled
R/W
0
TABLE 42: MICROPROCESSOR REGISTER #131, BIT DESCRIPTION
SL_1
SL_0
0
1
0
1
Slicer Mode
Normal
Decrease by 5% from Normal
Increase by 5% from Normal
Normal
EQG_1
EQG_0
0
1
0
1
Equalizer Gain
Normal
Reduce Gain by 1 dB
Reduce Gain by 3 dB
Normal
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